# US 8,772,100 B2 · Structure and method for forming a low gate resistance high-K metal gate transistor device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,772,100 B2
- Document ID: US8772100B2
- Status: Granted
- Kind: B2
- Application number: 13/654,987
- Filed: 2012-10-18
- Published: 2014-04-24
- Granted: 2014-07-08
- Earliest claimed: 2012-10-18
- Assignees: GLOBAL FOUNDRIES Inc.
- Applicants: GLOBALFOUNDRIES Inc.
- Inventors: Jingyan Huang; Keith Kwong Hon Wong
- Web page: https://patentgrep.com/patent/US8772100B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 64/68: characterised by the insulator, e.g. by the gate insulator
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A low gate resistance high-k metal gate transistor device is formed by providing a set of gate stacks (e.g., replacement metal gate (RMG) stacks) in a trench on a silicon substrate. The gate stacks in the trench may have various layers such as: a high-k layer formed over the substrate; a barrier layer (formed over the high-k layer; a p-type work function (pWF) layer formed over the barrier layer; and an n-type work function (nWF) layer formed over the pWF layer. The nWF layer will be subjected to a nitrogen containing plasma treatment to form a nitridized nWF layer on the top surface, and an Al containing layer will then be applied over the gas plasma treated layer. By utilizing a gas plasma treatment, the gap within the trench may remain wider, and thus allow for improved Al fill and reflow at high temperature (400° C.-480° C.) subsequently applied thereto.

## Claims

### Claim 1

A method for forming a low gate resistance high-k metal gate transistor device, comprising:
forming a set of gate stacks in a trench over a substrate, the set of gate stacks having an initial n-type work function (nWF) layer on a top surface of the set of gate stacks;
nitridizing the initial nWF layer with a nitrogen containing gas plasma, thereby forming a nitridized nWF layer at the top surface; and
applying an aluminum (Al) containing layer over the nitridized nWF layer and reflowing the device to fill the trench.

### Claim 2 (depends on 1)

The method of claim 1, the set of gate stacks comprising a set of replacement metal gate stacks (RMGs).

### Claim 3 (depends on 1)

The method of claim 1, the forming of the set of gate stacks comprising:
forming a high-k dielectric layer over the substrate;
forming a barrier layer over the high-k layer;
forming a p-type work function (pWF) layer over the barrier layer and the nWF layer over the pWF layer to yield a PFET transistor device; and
forming the nWF layer over the barrier for a NFET transistor device.

### Claim 4 (depends on 1)

The method of claim 1, wherein the nitridizing the initial nWF layer further comprises applying a plasma treatment over the initial nWF layer in the presence of a nitrogen (N2) gas or an ammonia (NH3) gas.

### Claim 5 (depends on 4)

The method of claim 4, wherein the nitridizing the initial nWF metal is carried out with plasma treatment at power range of about 100W-4000W, at a temperature range of about 25° C. to about 400° C., and at a pressure range of about 0.01-5 Torr.

### Claim 6 (depends on 1)

The method of claim 1, wherein the applying Al containing layer is carried out through chemical vapor deposition (CVD) or physical vapor deposition (PVD) approach; and Al containing layer comprising Al or Al—Ti alloy.

### Claim 7 (depends on 1)

The method of claim 1, wherein reflowing is performed at a high temperature range of about 400° C. to 480° C.

### Claim 8

A method for forming a low gate resistance high-k metal gate transistor device, comprising:
forming a set of gate stacks in a trench over a substrate, the set of gate stacks having a n-type work function (nWF) layer along a top surface;
applying a gas plasma over the n-type work function (nWF) layer of the set of gate stacks;
forming a metal layer over the gas plasma treated layer; and
applying a temperature in a range of about 400° C. to about 480° C. to the device to cause a reflow of the metal layer.

### Claim 9 (depends on 8)

The method of claim 8, the forming of the set of gate stacks comprising:
forming a high-k dielectric layer over the substrate;
forming a barrier layer over the high-k layer;
forming a p-type work function (pWF) layer over the barrier layer and the nWF layer over the pWF layer to yield a PFET transistor device; and
forming the nWF layer over the barrier for a NFET transistor device.

### Claim 10 (depends on 8)

The method of claim 8, the gas plasma comprising a nitrogen containing gas plasma.