# US 8,772,097 B2 · Method for fabricating a field effect transistor, and field effect transistor

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- Number: US 8,772,097 B2
- Document ID: US8772097B2
- Status: Granted
- Kind: B2
- Application number: 11/559,572
- Filed: 2006-11-14
- Published: 2007-05-24
- Granted: 2014-07-08
- Earliest claimed: 2005-11-14
- Assignees: Infineon Technologies AG
- Applicants: Luis-Felipe Giles; Frank Lau; Rainer Liebmann
- Inventors: Luis-Felipe Giles; Frank Lau; Rainer Liebmann
- Web page: https://patentgrep.com/patent/US8772097B2

## CPC

- H10D 30/798: {being provided in or under the channel regions}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 30/225: {of a molecular ion, e.g. decaborane}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

In a method for fabricating a field effect transistor, a first source/drain region and a second source/drain region are formed in a substrate. A channel region is formed between the first source/drain region and the second source/drain region. A gate region is formed on the channel region. Micro-cavities are formed in the substrate at least below the channel region, and the micro-cavities are oxidized.

## Claims

### Claim 1

A method for fabricating a field effect transistor, comprising:
forming a first source/drain region and a second source/drain region in a substrate;
forming a channel region between the first source/drain region and the second source/drain region;
forming a gate region on the channel region;
forming micro-cavities in the substrate below the channel region and laterally between the first source/drain region and the second source/drain region;
oxidizing the micro-cavities to form discontinuous, oxidized micro-cavities below the channel region and laterally between the first source/drain region and the second source/drain region; and
doping the first source/drain region and the second source/drain region after the micro-cavities are oxidized, to thereby form a field effect transistor comprising the discontinuous, oxidized micro-cavities below the channel region and laterally between the first source/drain region and the second source/drain region.

### Claim 2 (depends on 1)

The method as claimed in claim 1, wherein the step of forming the micro-cavities comprises:
forming micro-platelets in the substrate, and
forming the micro-cavities from the micro-platelets.

### Claim 3 (depends on 2)

The method as claimed in claim 2, wherein the micro-platelets are elongated along a plane parallel to the surface of the substrate.

### Claim 4 (depends on 2)

The method as claimed in claim 2, wherein the step of forming the micro-cavities comprises implanting light ions into the substrate so that the micro-platelets are formed in the substrate.

### Claim 5 (depends on 2)

The method as claimed in claim 2, wherein the step of forming the micro-cavities comprises thermally treating the substrate with the micro-platelets to form the micro-cavities.

### Claim 6 (depends on 5)

The method as claimed in claim 5, wherein the step of thermally treating the substrate with the micro-platelets comprises heating the substrate to a temperature of between 600° C. and 800° C.

### Claim 7 (depends on 5)

The method as claimed in claim 5, wherein the step of thermally treating the substrate with the micro-platelets comprises heating the substrate for a duration of between 10 minutes and 2 hours.

### Claim 8 (depends on 5)

The method as claimed in claim 5, wherein the step of forming the micro-cavities further comprises thermally treating the substrate a second time to effect a ripening process of the micro-cavities.

### Claim 9 (depends on 8)

The method as claimed in claim 8, wherein the step of thermally treating the substrate a second time comprises heating the substrate to a temperature between 1000° C. and 1300° C.

### Claim 10 (depends on 9)

The method as claimed in claim 9, wherein the step of thermally treating the substrate a second time comprises heating the substrate for a duration of between 1 μs and 1 s.

### Claim 11 (depends on 1)

The method as claimed in claim 1, wherein the step of forming the micro-cavities comprises implanting light ions into the substrate.

### Claim 12 (depends on 11)

The method as claimed in claim 11, wherein the light ions are at least one of the types of light ions selected from the group consisting of H2+ ions, He+ ions, F+ ions, Ne+ ions, Cl+ ions, and Ar+ ions.

### Claim 13 (depends on 11)

The method as claimed in claim 11, wherein the light ions are implanted with an implantation dose of between 1015 cm−2 and 4×1017 cm−2.

### Claim 14 (depends on 11)

The method as claimed in claim 11, wherein the light ions used during the implantation have an energy of between 10 keV and 150 keV.

### Claim 15 (depends on 11)

The method as claimed in claim 11, wherein the light ions are implanted using a mask.

### Claim 16 (depends on 1)

The method as claimed in claim 1, wherein the step of oxidizing the micro-cavities comprises:
oxidizing the micro-cavities via a high-temperature treatment; and
introducing oxygen into the micro-cavities.

### Claim 17 (depends on 16)

The method as claimed in claim 16, wherein the step of oxidizing the micro-cavities via a high-temperature treatment comprises heating the substrate to a temperature of between 1000° C. and 1350° C.

### Claim 18 (depends on 17)

The method as claimed in claim 17, wherein the step of oxidizing the micro-cavities via a high-temperature treatment comprises heating the substrate for a duration of between 30 minutes and 2 hours.

### Claim 19 (depends on 16)

The method as claimed in claim 16, wherein the step of introducing oxygen into the micro-cavities comprises introducing oxygen into the micro-cavities by thermal indiffusing oxygen or by implanting oxygen.

### Claim 20 (depends on 1)

The method as claimed in claim 1, wherein a silicon substrate is used as the substrate.

### Claim 21 (depends on 20)

The method as claimed in claim 20, wherein a (100) silicon substrate or a (111) silicon substrate is used as the substrate.

### Claim 22 (depends on 20)

The method as claimed in claim 20, wherein the step of oxidizing the micro-cavities results in a formation of silicon dioxide precipitates, which produce a tensile stress field.

### Claim 23 (depends on 1)

The method as claimed in claim 1, wherein the field effect transistor is an n-MOS field effect transistor with an n-doped first source/drain region, an n-doped second source/drain region, and a p-doped channel region.

### Claim 24 (depends on 23)

The method as claimed in claim 23, further comprising forming a nitride layer on at least one region selected from the group of regions consisting of a partial region of the first source/drain region, a partial region of the second source/drain region, and a partial region of the gate region.

### Claim 25 (depends on 1)

A field effect transistor fabricated using the method of claim 1.

### Claim 26

A method for fabricating a field effect transistor, comprising:
forming a first and a second source/drain region in a substrate;
forming a channel region between the first and the second source/drain region;
forming a gate region on the channel region;
forming micro-cavities in the substrate below the channel region by implanting light ions into the substrate region laterally between the first source/drain region and the second source/drain region;
oxidizing the micro-cavities to form discontinuous, oxidized micro-cavities below the channel region and laterally between the first source/drain region and the second source/region; and
doping the first source/drain region and the second source/drain region after the micro-cavities are oxidized, to thereby form a field effect transistor comprising the discontinuous, oxidized micro-cavities below the channel region and laterally between the first source/drain region and the second source/drain region.

### Claim 27

A method for fabricating a field effect transistor, comprising:
forming a first and a second source/drain region in a substrate;
forming a channel region between the first and the second source/drain region;
forming a gate region on the channel region;
forming micro-cavities in the substrate below the channel region and laterally between the first source/drain region and the second source/drain region;
oxidizing the micro-cavities to form, below the channel region and laterally between the first source/drain region and the second source/drain region, discontinuous micro-cavities having silicon dioxide precipitates; and
doping the first source/drain region and the second source/drain region after the micro-cavities are oxidized, to thereby form a field effect transistor comprising the discontinuous, oxidized micro-cavities below the channel region and laterally between the first source/drain region and the second source/drain region,
wherein a tensile stress field is produced at least in a partial region of the channel region.