# US 8,772,095 B2 · Method of manufacturing semiconductor device using stress memorization technique

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- Number: US 8,772,095 B2
- Document ID: US8772095B2
- Status: Granted
- Kind: B2
- Application number: 13/495,062
- Filed: 2012-06-13
- Published: 2013-05-09
- Granted: 2014-07-08
- Earliest claimed: 2011-11-04
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Seok-Hoon Kim; Sang-Su Kim; Chung-Geun Koh; Sun-Ghil Lee; Jin-Yeong Joe
- Inventors: Seok-Hoon Kim; Sang-Su Kim; Chung-Geun Koh; Sun-Ghil Lee; Jin-Yeong Joe
- Web page: https://patentgrep.com/patent/US8772095B2

## CPC

- H10P 30/204: {into Group IV semiconductors}
- H10D 30/796: {having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 30/208: {of electrically inactive species}
- H10P 30/226: {at a temperature lower than room temperature}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The manufacturing a semiconductor device includes providing a substrate supporting a gate electrode, amorphizing and doping the source/drain regions located on both sides of the gate electrode by performing a pre-amorphization implant (PAI) process and implanting C or N into the source/drain regions in or separately from the PAI process, forming a stress inducing layer on the substrate to cover the amorphized source/drain regions, and subsequently recrystallizing the source/drain regions by annealing the substrate. The stress inducing layer may then be removed. Also, the C or N may be implanted into the entirety of the source/drain regions after the regions have been amorphized, or only into upper portions of the amorphized source/drain regions.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
providing a structure that includes a substrate, and a gate electrode at an upper part of the substrate, the gate electrode having opposite sides;
forming doped amorphous source/drain regions to the sides of the gate electrode, respectively, such that the amorphous source/drain regions are spaced from each other across a channel region of the substrate;
subsequently annealing the substrate to recrystalize the doped amorphous source/drain regions; and
before the substrate is annealed, forming over the doped amorphous source/drain regions of the substrate a stress inducing layer that stresses the doped amorphous source/drain regions during the recrystallizating of the doped amorphous source/drain regions, and
wherein the forming of the doped amorphous source/drain regions comprises a pre-amorphization implantation (PAI) process that amorphizes the source/drain regions to the sides of the gate electrode, and implanting, into the amorphized source/drain regions, impurities that will minimize differences between crystal growth rates in different crystallographic directions during the annealing of the substrate.

### Claim 2 (depends on 1)

The method of claim 1, wherein the implanting comprises implanting C or N into the substrate.

### Claim 3 (depends on 2)

The method of claim 2, wherein the energy level at which the C or N is implanted is within a range of 5 to 10 KeV.

### Claim 4 (depends on 2)

The method of claim 2, wherein the pre-amorphization implantation (PAI) process comprises implanting Si or Ge into the substrate to form amorphous source/drain regions of the substrate, and
the implanting of impurities comprises doping the amorphous source/drain regions with the C or N.

### Claim 5 (depends on 4)

The method of claim 4, wherein the energy level at which the Ge or Si is implanted is in a range of 10 to 35 KeV.

### Claim 6 (depends on 1)

The method of claim 1, wherein the annealing of the substrate is performed within a temperature range of 450 to 800° C.

### Claim 7 (depends on 1)

The method of claim 1, further comprising removing the stress inducing layer after the doped amorphous source/drain regions have been recrystallized.

### Claim 8

A method of manufacturing a semiconductor device, the method comprising:
providing a structure that includes a substrate, and a gate electrode disposed on an upper part of the substrate, the gate electrode having opposite sides, wherein the substrate has source/drain regions located to the sides of the gate electrode, respectively, and a channel region interposed between the source/drain regions; and
inducing stress in the channel region of the substrate by growing crystals in the source/drain regions at substantially the same rates in both <001> and <110> crystallographic directions substantially perpendicular and parallel to an upper surface of substrate, respectively,
wherein the inducing of stress in the channel region comprises:
performing a pre-amorphization implantation (PAI) process that amorphizes the source/drain regions,
doping the source/drain regions amorphized by the PAI process to form doped amorphous source/drain regions of the substrate,
forming over the doped amorphous source/drain regions of the substrate a stress inducing layer, and
subsequently subjecting the amorphous source/drain regions to a solid phase epitaxial (SPE) growth process that recrystallizes the amorphous source/drain regions, the stress inducing layer stressing the doped amorphous source/drain regions during the recrystallizating of the doped amorphous source/drain regions.

### Claim 9 (depends on 8)

The method of claim 8, wherein the doping comprises implanting C or N into the source/drain regions, and the SPE growth process comprises annealing the substrate.

### Claim 10 (depends on 9)

The method of claim 9, wherein the energy level at which the C or N is implanted is within a range of 5 to 10 KeV.

### Claim 11 (depends on 9)

The method of claim 9, wherein the pre-amorphization implantation (PAI) process comprises implanting Si or Ge into the substrate to form the amorphous source/drain regions of the substrate, and
the doping comprises doping the amorphous source/drain regions with the C or N.

### Claim 12 (depends on 11)

The method of claim 11, wherein the energy level at which the Ge or Si is implanted is in a range of 10 to 35 KeV.

### Claim 13 (depends on 8)

The method of claim 8, wherein the SPE process comprises annealing the substrate within a temperature range of 450 to 800° C.

### Claim 14 (depends on 8)

The method of claim 8, further comprising removing the stress inducing layer after the SPE process has been carried out.

### Claim 15

A method of manufacturing a semiconductor device, the method comprising:
providing a structure that includes a substrate, and a gate electrode at an upper part of the substrate, the gate electrode having opposite sides, wherein the substrate has source/drain regions located to the sides of the gate electrode;
performing a pre-amorphization implantation (PAI) process that amorphizes the source/drain regions;
implanting C or N into the amorphized source/drain regions;
forming a stress inducing layer that covers the substrate;
subsequently recrystallizing the amorphized source/drain regions by annealing the substrate; and
removing the stress inducing layer after the substrate has been annealed.

### Claim 16 (depends on 15)

The method of claim 15, wherein the amorphizing of the source/drain regions comprises implanting Ge or Si into the source/drain regions.

### Claim 17 (depends on 16)

The method of claim 16, wherein the energy level at which the Ge or Si is implanted is in a range of 10 to 35 KeV, and the energy level at which the C or N is implanted is within a range of 5 to 10 KeV.

### Claim 18 (depends on 15)

The method of claim 15, wherein the C or N is implanted at a dosage of 1E14 to 5E15 atoms/cm2.

### Claim 19 (depends on 15)

The method of claim 15, further comprising forming a buffer oxide film over the substrate before the stress inducing layer is formed, and wherein the stress inducing layer is formed over the buffer oxide film and comprises silicon nitride.

### Claim 20 (depends on 15)

The method of claim 15, wherein the C or N is implanted into only part of each of the source/drain regions.

### Claim 21 (depends on 15)

The method of claim 15, wherein the annealing of the substrate is performed within a temperature range of 450 to 800° C.

### Claim 22 (depends on 15)

The method of claim 15, further comprising conformally forming a spacer film over the substrate before the the PAI process is preformed.

### Claim 23 (depends on 15)

The method of claim 15, wherein the stress inducing layer induces tensile stress in the amorphized source/drain regions during the annealing of the substrate, and further comprising implanting n-conductivity type impurities into the source/drain regions such that the semiconductor device comprises an n-channel metal oxide semiconductor (nMOS) transistor.