# US 8,772,093 B2 · Manufacturing method of semiconductor device

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- Number: US 8,772,093 B2
- Document ID: US8772093B2
- Status: Granted
- Kind: B2
- Application number: 13/717,806
- Filed: 2012-12-18
- Published: 2013-05-23
- Granted: 2014-07-08
- Earliest claimed: 2009-07-31
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co. Ltd.
- Inventors: Shunpei Yamazaki; Miyuki Hosoba; Junichiro Sakata; Hideaki Kuwabara
- Web page: https://patentgrep.com/patent/US8772093B2

## CPC

- G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 30/6704: {having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D 86/0223: {comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials}
- H10D 86/411: {characterised by materials, geometry or structure of the substrates}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- G02F 1/1339: Gaskets; Spacers; Sealing of cells
- G02F 1/134336: {Matrix}
- G02F 1/1345: Conductors connecting electrodes to cell terminals
- G02F 1/13606: {having means for reducing parasitic capacitance}
- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- G02F 1/167: by electrophoresis
- G02F 2201/123: pixel
- G09G 3/344: {based on particles moving in a fluid or in a gas, e.g. electrophoretic devices (electrophoretic devices per se G02F1/167)}
- G09G 3/3677: {suitable for active matrices only}
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- H10K 59/1213: {the pixel elements being TFTs}
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.

## Claims

### Claim 1

A method of forming a semiconductor device, comprising the steps of:
forming a gate electrode layer;
forming a gate insulating layer over the gate electrode layer;
forming a semiconductor layer over the gate insulating layer;
forming a first insulating layer in contact with and covering a peripheral portion and a central portion of the semiconductor layer, the central portion of the semiconductor layer overlapping with the gate electrode layer;
forming a source electrode layer and a drain electrode layer over the first insulating layer and in electrical contact with the semiconductor layer in an region comprised between the peripheral portion and the central portion of the semiconductor layer; and
forming a second insulating layer on and in contact with the first insulating layer, the source electrode layer, the drain electrode layer, and the semiconductor layer.

### Claim 2 (depends on 1)

The method of forming a semiconductor device according to claim 1,
wherein the first insulating layer comprises an oxide.

### Claim 3 (depends on 1)

The method of forming a semiconductor device according to claim 1,
wherein the second insulating layer comprises an oxide.

### Claim 4 (depends on 1)

The method of forming a semiconductor device according to claim 1, further comprising the steps of:
forming a first electrically conductive layer from a same layer as the gate electrode layer;
forming a third insulating layer on and in contact with the gate insulating layer; and
forming a second electrically conductive layer from a same layer as the source electrode layer, over the third insulating layer.

### Claim 5 (depends on 1)

The method of forming a semiconductor device according to claim 1, further comprising the steps of:
forming a first electrically conductive layer from a same layer as the source electrode layer;
forming a protective insulating layer on and in contact with the gate insulating layer;
forming a planarizing insulating layer over the protective insulating layer; and
forming a second electrically conductive layer on and in direct contact with an upper surface of the protective insulating layer, and in contact with the first electrically conductive layer.

### Claim 6

A method of forming a semiconductor device, comprising the steps of:
forming a gate electrode layer;
forming a gate insulating layer over the gate electrode layer;
forming an oxide semiconductor layer over the gate insulating layer;
dehydrating or dehydrogenating the oxide semiconductor layer;
forming an oxide insulating layer being in contact with part of the oxide semiconductor layer and covering a peripheral portion and a side surface of the oxide semiconductor layer;
forming a source electrode layer and a drain electrode layer over the oxide insulating layer and in electrical contact with the oxide semiconductor layer; and
forming an insulating layer on and in contact with the oxide insulating layer, the source electrode layer, the drain electrode layer, and the oxide semiconductor layer,
wherein the oxide semiconductor layer is prevented from being exposed to air between the step of dehydrating or dehydrogenating the oxide semiconductor layer and the step of forming the oxide insulating layer, so as to prevent water or hydrogen contamination.

### Claim 7 (depends on 6)

The method of forming a semiconductor device according to claim 6,
wherein the oxide insulating layer is a silicon oxide film or an aluminum oxide film.

### Claim 8 (depends on 6)

The method of forming a semiconductor device according to claim 6,
wherein the insulating layer is a silicon oxide film or an aluminum oxide film.

### Claim 9 (depends on 6)

The method of forming a semiconductor device according to claim 6, further comprising the steps of:
forming a first electrically conductive layer from a same layer as the gate electrode layer;
forming a second oxide insulating layer above and in contact with the gate insulating layer; and
forming a second electrically conductive layer from a same layer as the source electrode layer, over the second oxide insulating layer.

### Claim 10 (depends on 6)

The method of forming a semiconductor device according to claim 6, further comprising the steps of:
forming a first electrically conductive layer from a same layer as the source electrode layer;
forming a protective insulating layer on and in contact with the gate insulating layer;
forming a planarizing insulating layer over the protective insulating layer; and
forming a second electrically conductive layer on and in direct contact with an upper surface of the protective insulating layer, and in contact with the first electrically conductive layer.

### Claim 11

A method of forming a semiconductor device, comprising the steps of:
forming a gate electrode layer;
forming a gate insulating layer over the gate electrode layer;
forming an oxide semiconductor layer over the gate insulating layer;
dehydrating or dehydrogenating the oxide semiconductor layer;
forming an oxide insulating layer on the oxide semiconductor layer;
etching the oxide insulating layer so as to form a first opening and a second opening, in the oxide insulating layer, each overlapping with the oxide semiconductor layer with therebetween a remaining portion of the oxide insulating layer overlapping with the gate electrode layer, when seen in a cross-section view;
forming a source electrode layer and a drain electrode layer over the oxide insulating layer and in electrical contact with the oxide semiconductor layer through the first opening and the second opening; and
forming an insulating layer on and in contact with the oxide insulating layer, the source electrode layer, the drain electrode layer, and the oxide semiconductor layer.

### Claim 12 (depends on 11)

The method of forming a semiconductor device according to claim 11,
wherein the oxide insulating layer is a silicon oxide film or an aluminum oxide film.

### Claim 13 (depends on 11)

The method of forming a semiconductor device according to claim 11,
wherein the insulating layer is a silicon oxide film or an aluminum oxide film.

### Claim 14 (depends on 11)

The method of forming a semiconductor device according to claim 11, further comprising the steps of:
forming a first electrically conductive layer from a same layer as the gate electrode layer;
forming a second oxide insulating layer on and in contact with the gate insulating layer; and
forming a second electrically conductive layer from a same layer as the source electrode layer, over the second oxide insulating layer.

### Claim 15 (depends on 11)

The method of forming a semiconductor device according to claim 11, further comprising the steps of:
forming a first electrically conductive layer from a same layer as the source electrode layer;
forming a protective insulating layer on and in contact with the gate insulating layer;
forming a planarizing insulating layer over the protective insulating layer; and
forming a second electrically conductive layer on and in direct contact with an upper surface of the protective insulating layer, and in contact with the first electrically conductive layer.