# US 8,772,087 B2 · Method and apparatus for semiconductor device fabrication using a reconstituted wafer

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- Number: US 8,772,087 B2
- Document ID: US8772087B2
- Status: Granted
- Kind: B2
- Application number: 12/604,153
- Filed: 2009-10-22
- Published: 2011-04-28
- Granted: 2014-07-08
- Earliest claimed: 2009-10-22
- Assignees: Infineon Technologies AG
- Applicants: Hans-Joachim Barth; Matthias Hierlemann
- Inventors: Hans-Joachim Barth; Matthias Hierlemann
- Web page: https://patentgrep.com/patent/US8772087B2

## CPC

- H10W 74/016: {using moulds}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/68: Shapes or dispositions thereof
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/00: Package configurations
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/0198: {batch processes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9413: {on encapsulations}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Method and apparatus for semiconductor device fabrication using a reconstituted wafer is described. In one embodiment, diced semiconductor chips are placed within openings on a frame. A reconstituted wafer is formed by filling a mold compound into the openings. The mold compound is formed around the chips. Finished dies are formed within the reconstituted wafer. The finished dies are separated from the frame.

## Claims

### Claim 1

A method of fabricating a semiconductor device, the method comprising:
placing a frame comprising through openings over a carrier;
placing diced semiconductor chips within the through openings in the frame, wherein a chip placed within one through opening in the frame is separated from another chip placed within an adjacent through opening in the frame by a portion of the frame;
forming a reconstituted wafer by filling a mold compound into the through openings, the mold compound being formed around the chips;
separating the frame with the reconstituted wafer from the carrier;
after separating the frame with the reconstituted wafer from the carrier, forming finished dies within the frame with the reconstituted wafer by forming a redistribution layer comprising redistribution lines; and
after forming the redistribution layer, separating the finished dies from the frame while keeping the frame intact.

### Claim 2 (depends on 1)

The method of claim 1, wherein separating the finished dies from the frame comprises removing the finished dies from the reconstituted wafer without damaging the frame.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
dicing another semiconductor wafer to form further chips; and
after separating the finished dies from the frame, repeating with the further chips the steps of placing, forming a reconstituted wafer, forming finished dies, and separating.

### Claim 4 (depends on 1)

The method of claim 1, wherein the through openings have tapered sidewalls.

### Claim 5 (depends on 1)

The method of claim 1, further comprising placing the frame on an adhesive tape, a first surface of the chips having active devices disposed on the adhesive tape, the adhesive tape supporting the chips in the through openings.

### Claim 6 (depends on 5)

The method of claim 5, wherein forming finished dies within the reconstituted wafer comprises:
removing the adhesive tape to expose the first surface;
forming a first dielectric layer over the first surface;
patterning the first dielectric layer for redistribution layer;
forming the redistribution layer in the patterned first dielectric layer;
forming a second dielectric layer over the first dielectric layer;
patterning the second dielectric layer for contact pads; and
forming solder bumps.

### Claim 7 (depends on 5)

The method of claim 5, wherein the through openings of the frame comprise tapered sidewalls, the through openings having a larger diameter at a bottom surface adjacent the adhesive tape than at a distance about midway between an opposite top surface of the frame and the bottom surface.

### Claim 8 (depends on 7)

The method of claim 7, wherein the through openings have a larger diameter adjacent the top surface of the frame than at a distance about midway between the top and the bottom surfaces of the frame.

### Claim 9 (depends on 1)

The method of claim 1, wherein the mold compound is disposed over a back surface of the chips, an opposite front surface comprising active devices.

### Claim 10 (depends on 1)

The method of claim 1, wherein the redistribution layer and solder balls are formed over the chip area and over the mold.

### Claim 11 (depends on 1)

The method of claim 1, wherein the frame comprises a material having a coefficient of thermal expansion more than about 0.5 times a coefficient of thermal expansion of the chips but less than about 2 times the coefficient of thermal expansion of the chips.

### Claim 12 (depends on 11)

The method of claim 11, wherein the frame comprises silicon.

### Claim 13 (depends on 1)

The method of claim 1, wherein the separation between the through openings in the frame is about 0.2% to about 5% of the diameter of the reconstituted wafer.

### Claim 14 (depends on 1)

The method of claim 1, wherein a volume fraction of the mold compound in the reconstituted wafer is less than 0.5.

### Claim 15 (depends on 1)

A semiconductor device formed by the method of claim 1.

### Claim 16

A method of fabricating a semiconductor device, the method comprising:
placing a first plurality of diced chips in a frame having through openings, wherein a chip placed within one through opening in the frame is separated from another chip placed within an adjacent through opening in the frame by a portion of the frame;
forming a first reconstituted wafer by filling a mold compound into the through openings, the mold compound being formed around the chips, wherein a height of the through openings is greater than a thickness of each of the first plurality of diced chips, wherein a portion of the mold compound covers a major surface of the first plurality of diced chips after forming the first reconstituted wafer;
forming a first plurality of finished dies within the reconstituted wafer by forming a first redistribution layer comprising first redistribution metal lines over the first plurality of diced chips and the frame; and
after forming the first redistribution layer comprising first redistribution metal lines, separating the first plurality of finished dies from the frame,
after separating the first plurality of finished dies from the frame, placing a second plurality of diced chips in the through openings of the frame;
forming a second reconstituted wafer by filling the mold compound into the through openings;
forming a second plurality of finished dies within the second reconstituted wafer by forming a second redistribution layer comprising second redistribution metal lines over the second plurality of diced chips and the frame; and
after forming the second redistribution layer comprising second redistribution metal lines, separating the second plurality of finished dies from the frame.

### Claim 17 (depends on 16)

The method of claim 16, wherein the frame comprises a material having a coefficient of thermal expansion about the same as the coefficient of thermal expansion of the first plurality of diced chips.

### Claim 18 (depends on 16)

The method of claim 16, further comprising placing the frame on an adhesive tape before placing the first plurality of diced chips in the frame, a first surface of the first plurality of diced chips having active devices disposed on the adhesive tape, wherein the adhesive tape supports the first plurality of diced chips.

### Claim 19 (depends on 16)

The method of claim 16, wherein a thickness of the frame is about the same as a thickness of the first plurality of finished dies.

### Claim 20 (depends on 1)

The method of claim 1, further comprising discarding the frame after separating the finished dies from the frame.

### Claim 21 (depends on 1)

The method of claim 1, wherein the diced semiconductor chips comprise a first chip and a second chip, and wherein placing the diced semiconductor chips within through openings in a frame comprise placing the first chip and the second chip within a same opening.

### Claim 22 (depends on 21)

The method of claim 21, wherein forming the finished dies comprises coupling the first chip with the second chip through a conductive layer.

### Claim 23

A method of fabricating a semiconductor device, the method comprising:
placing a reusable frame over a carrier;
placing diced semiconductor chips within through openings in the reusable frame, wherein a chip placed within one through opening in the reusable frame is separated from another chip placed within an adjacent through opening in the reusable frame by a portion of the reusable frame;
forming a reconstituted wafer by filling a mold compound into the through openings, the mold compound being formed around the chips;
separating the reusable frame with the reconstituted wafer from the carrier;
after separating the reusable frame with the reconstituted wafer from the carrier, forming metallization layers over the reconstituted wafer to form finished dies; and
after forming the metallization layers, separating the finished dies from the reusable frame while keeping the reusable frame intact.

### Claim 24 (depends on 1)

The method of claim 1, wherein forming finished dies within frame with the reconstituted wafer further comprises forming solder balls.

### Claim 25 (depends on 1)

The method of claim 1, wherein forming finished dies within frame with the reconstituted wafer further comprises:
depositing a conductive layer overlapping with portions of the frame; and
etching the conductive layer to expose the frame.

### Claim 26 (depends on 23)

The method of claim 23, wherein forming metallization layers over the reconstituted wafer to form finished dies comprises:
forming redistribution metal lines comprising a conductive liner over the dies and portions of the reusable frame, and
etching the portions of the conductive liner from over the reusable frame.