# US 8,772,086 B2 · Disabling electrical connections using pass-through 3D interconnects and associated systems and methods

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,772,086 B2
- Document ID: US8772086B2
- Status: Granted
- Kind: B2
- Application number: 13/850,803
- Filed: 2013-03-26
- Published: 2013-08-22
- Granted: 2014-07-08
- Earliest claimed: 2008-05-15
- Assignees: Micron Technology, Inc.
- Applicants: Russell D. Slifer; Micron Technology, Inc.
- Inventors: Jeffery W. Janzen; Michael Chaine; Kyle K. Kirby; William M. Hiatt
- Web page: https://patentgrep.com/patent/US8772086B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 84/01: Manufacture or treatment
- H10D 89/60: Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0238: {comprising etching via holes through pads or through electrodes}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses
- H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60)
- H10W 42/80: protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60)
- H10W 72/00: Interconnections or connectors in packages
- H10W 90/00: Package configurations
- H10W 95/00: Packaging processes not covered by the other groups of this subclass
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/07253: {changes in shapes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/237: {Multiple bump connectors having different shapes}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.

## Claims

### Claim 1

A microelectronic workpiece, comprising:
a substrate having a front side and a backside;
a first circuit and a second circuit carried by the substrate;
an interconnect extending through the substrate and electrically coupled to the first circuit, the interconnect having a metal layer electrically coupling the front side of the substrate with the backside of the substrate;
a dielectric liner along the interconnect between the interconnect and the substrate wherein the dielectric liner electrically isolates the first circuit from the second circuit; and
an electrostatic discharge (ESD) device electrically coupled to the second circuit such that the ESD device is electrically isolated from the interconnect.

### Claim 2 (depends on 1)

The microelectronic workpiece of claim 1 wherein the dielectric liner separates the interconnect from the second circuit.

### Claim 3 (depends on 1)

The microelectronic workpiece of claim 1 wherein the first circuit includes an integrated circuit and the second circuit includes a component of the integrated circuit.

### Claim 4 (depends on 1)

The microelectronic workpiece of claim 1 wherein the first circuit includes an integrated circuit and the second circuit includes an electrostatic discharge device.

### Claim 5

An interconnect structure, comprising:
a first metal layer of a microelectronic die;
a second metal layer of the die being separated from the first metal layer by at least one passivation layer;
a metal interconnect extending through the die from, at least, a surface at a front side of the die to a surface at a backside of the die, the interconnect also extending through the first metal layer and the second metal layer;
a dielectric layer at least partially lining the interconnect and electrically isolating the first and second metal layers from one another; and
wherein the die carries an electrostatic discharge (ESD) device, the second metal layer provides a conduction path to the ESD device, and the dielectric layer electrically isolates the conduction path from the first metal layer.

### Claim 6 (depends on 5)

The interconnect structure of claim 5 wherein the die carries an integrated circuit, the first metal layer provides a conduction path between the integrated circuit and the interconnect, and the dielectric layer electrically isolates a conduction path between the integrated circuit and the interconnect.

### Claim 7 (depends on 5)

The interconnect structure of claim 5 wherein the first and second metal layers are located within a microelectronic substrate carried by the die.

### Claim 8 (depends on 5)

The interconnect structure of claim 5 wherein the first and second metal layers are located within a redistribution layer attached to the surface at the front side of the die.

### Claim 9

A method of manufacturing a stacked system of microelectronic dies comprising:
disabling a first electrostatic discharge (ESD) device from first internal circuitry of a first microelectronic die by forming at least one dielectric liner;
attaching a second microelectronic die to the first die in a stacked arrangement, wherein the second die has second internal circuitry and a second ESD device electrically coupled to the second internal circuitry, and wherein attaching the second die to the first die electrically couples the second ESD device to the first internal circuitry such that second ESD device protects the first internal circuitry and the second internal circuitry from electrostatic energy.

### Claim 10 (depends on 9)

The method of claim 9 wherein the first and second ESD devices are redundant such that disabling the first ESD device reduces overall capacitive loading and improves the signal integrity of the stacked first and second dies.

### Claim 11 (depends on 10)

The method of claim 10 wherein disabling the first ESD device comprises forming a hole in the first die that severs an electrical connection to the first ESD device.

### Claim 12 (depends on 11)

The method of claim 11, further comprising locating the hole at a bond pad and forming a conductive through-substrate interconnect in the hole, wherein the through-substrate interconnect is electrically connected to the second ESD device but is electrically isolated from the first ESD device.

### Claim 13

A method of manufacturing a microelectronic workpiece, the method comprising:
forming at least one dielectric liner in a microelectronic substrate that carries a first circuit and a second circuit electrically connected to each other via a conduction path in the substrate, the dielectric liner being formed through the conduction path to electrically disconnect the first circuit and the second circuit from each other.

### Claim 14 (depends on 13)

The method of claim 13 wherein the substrate includes a metal pad that is electrically coupled to the first circuit and the second circuit, and the forming of the dielectric liner in the substrate electrically isolates the second circuit from the metal pad after the hole is formed.

### Claim 15 (depends on 13)

The method of claim 13 wherein forming the dielectric liner includes removing conductive material from the substrate associated with one or more metal vias of the substrate.

### Claim 16 (depends on 13)

The method of claim 13, further comprising at least partially filling a hole with a metal, wherein the metal is adjacent to the dielectric liner.

### Claim 17 (depends on 13)

The method of claim 13 wherein the second circuit comprises an electrostatic discharge device.