# US 8,772,085 B2 · Integrated circuit package architecture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,772,085 B2 - Document ID: US8772085B2 - Status: Granted - Kind: B2 - Application number: 13/416,163 - Filed: 2012-03-09 - Published: 2012-06-28 - Granted: 2014-07-08 - Earliest claimed: 2009-07-31 - Assignees: Altera Corporation - Applicants: William Y. Hata - Inventors: William Y. Hata - Web page: https://patentgrep.com/patent/US8772085B2 ## CPC - H10W 90/00: Package configurations - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - Y10T 29/49126: Assembling bases - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract A packaging architecture for an integrated circuit is provided. The architecture includes a printed circuit board and a package substrate disposed on the printed circuit board. A first integrated circuit is disposed on a first surface of the package substrate. The package substrate is capable of supporting a second integrated circuit. The second integrated circuit is in electrical communication with a plurality of pads disposed on the first surface of the package substrate. Each of the plurality of pads is in electrical communication with the printed circuit board without communicating with the first integrated circuit. ## Claims ### Claim 1 A method of packaging an integrated circuit, comprising: coupling a first integrated circuit to a package substrate; coupling a second integrated circuit to the package substrate, the second integrated circuit disposed over the first integrated circuit; and coupling the package substrate to a printed circuit board such that the second integrated circuit communicates data to the first integrated circuit exclusively through the printed circuit board prior to being delivered to the first integrated circuit. ### Claim 2 (depends on 1) The method of claim 1, wherein the first integrated circuit is a programmable logic device and the second integrated circuit is a memory device storing a configuration for operation of the first integrated circuit. ### Claim 3 (depends on 2) The method of claim 2, wherein the second integrated circuit is programmed with the configuration prior to being coupled to the package substrate. ### Claim 4 (depends on 1) The method of claim 1 further comprising: shorting coupling traces from the second integrated circuit to dual purpose I/O pins of the first integrated circuit. ### Claim 5 (depends on 1) The method of claim 1, comprising: routing each landing pad on the package substrate designated for coupling with the second integrated circuit directly to the printed circuit board. ### Claim 6 (depends on 1) The method of claim 1, further comprising: coupling the second integrated circuit to the printed circuit board by a through via of the package substrate. ### Claim 7 (depends on 1) The method of claim 1, further comprising: programming the second integrated circuit; and placing the second integrated circuit on the package substrate, after the programming. ### Claim 8 (depends on 1) The method of claim 1, further comprising: placing the second integrated circuit on the package substrate; and programming the second integrated circuit after the placing. ### Claim 9 (depends on 1) The method of claim 1, further comprising: applying in system programming to the second integrated circuit, after the package substrate is coupled to the printed circuit board. ### Claim 10 (depends on 1) The method of claim 1, further comprising: coupling the second integrated circuit to the printed circuit board by a plated through hole of the package substrate. ### Claim 11 (depends on 1) The method of claim 1, further comprising: coupling the second integrated circuit to the printed circuit board by a metallization layer in the package substrate. ### Claim 12 A method of packaging an integrated circuit, comprising: coupling a first integrated circuit to a package substrate; placing a second integrated circuit above the first integrated circuit; coupling the second integrated circuit to the package substrate; coupling the first integrated circuit to a printed circuit board, by the package substrate; and coupling the second integrated circuit to the printed circuit board, by the package substrate, wherein all communication from the first integrated circuit to the second integrated circuit and from the second integrated circuit to the first integrated circuit occurs by way of the printed circuit board. ### Claim 13 (depends on 12) The method of claim 12, further comprising: storing, in the second integrated circuit, a configuration of the first integrated circuit, wherein the first integrated circuit includes a programmable logic device. ### Claim 14 (depends on 12) The method of claim 12, further comprising: programming the second integrated circuit with a configuration of the first integrated circuit, wherein the first integrated circuit includes a programmable logic device. ### Claim 15 (depends on 12) The method of claim 12, further comprising: designating a landing pad, on the package substrate, to couple with the second integrated circuit; and routing the landing pad to the printed circuit board, by the package substrate. ### Claim 16 (depends on 12) The method of claim 12, further comprising: coupling the second integrated circuit to a through via of the package substrate; and coupling the through via to the printed circuit board. ### Claim 17 (depends on 12) The method of claim 12, further comprising: programming a memory of the second integrated circuit, prior to coupling the second integrated circuit to the package substrate. ### Claim 18 (depends on 12) The method of claim 12, further comprising: programming a memory of the second integrated circuit, after coupling the second integrated circuit to the package substrate. ### Claim 19 (depends on 12) The method of claim 12, further comprising: applying in system programming to the second integrated circuit, by way of the printed circuit board and the package substrate. ### Claim 20 (depends on 12) The method of claim 12, further comprising: coupling the second integrated circuit to the printed circuit board by one of: a plated through hole of the package substrate, or a metallization layer of the package substrate.