# US 8,772,059 B2 · Inline method to monitor ONO stack quality > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,772,059 B2 - Document ID: US8772059B2 - Status: Granted - Kind: B2 - Application number: 13/430,631 - Filed: 2012-03-26 - Published: 2013-07-11 - Granted: 2014-07-08 - Earliest claimed: 2011-05-13 - Assignees: Cypress Semiconductor Corporation - Applicants: Yu Yang; Krishnaswamy Ramkumar - Inventors: Yu Yang; Krishnaswamy Ramkumar - Web page: https://patentgrep.com/patent/US8772059B2 ## CPC - H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors - H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors} - H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Embodiments of structures and methods for determining operating characteristics of a non-volatile memory transistor comprising a charge-storage-layer and a tunneling-layer are described. In one embodiment, the method comprises: forming on a substrate a structure including a nitrided tunneling-layer and a charge-storage-layer overlying the tunneling-layer comprising a first charge-storage layer adjacent to the tunneling-layer, and a second charge-storage layer overlying the first charge-storage layer, wherein the first charge-storage layer is separated from the second charge-storage layer by a anti-tunneling layer comprising an oxide; depositing a positive charge on the charge-storage-layer and determining a first voltage to establish a first leakage current through the charge-storage-layer and the tunneling-layer; depositing a negative charge on the charge-storage-layer and determining a second voltage to establish a second leakage current through the charge-storage-layer and the tunneling-layer; and determining a differential voltage by calculating a difference between the first and second voltages. ## Claims ### Claim 1 A method comprising: forming on a substrate a test structure including a tunneling-layer comprising a nitrided oxide and a charge-storage-layer overlying the tunneling-layer, the charge-storage-layer comprising a first charge-storage layer adjacent to the tunneling-layer, and a second charge-storage layer overlying the first charge-storage layer, wherein the first charge-storage layer is separated from the second charge-storage layer by a thin anti-tunneling layer comprising an oxide; depositing a positive charge at a first site on the uppermost surface of the charge-storage-layer and determining a positive tunneling voltage for the structure; depositing a negative charge at a second site on the uppermost surface of the charge-storage-layer and determining a negative tunneling voltage for the structure; determining a differential tunneling voltage by calculating a difference between the positive and negative tunneling voltages. ### Claim 2 (depends on 1) The method of claim 1, wherein the first charge-storage layer comprises nitride. ### Claim 3 (depends on 2) The method of claim 2, wherein the second charge-storage layer comprises a high K dielectric. ### Claim 4 (depends on 1) The method of claim 1, wherein the first site is proximal to the second site. ### Claim 5 (depends on 1) The method of claim 1, wherein forming the structure comprises forming the structure on a product substrate on which the non-volatile memory transistor is fabricated. ### Claim 6 A method comprising: forming on a substrate a test structure including a tunneling-layer comprising a nitrided oxide and a charge-storage-layer overlying the tunneling-layer, the charge-storage-layer comprising a first charge-storage layer adjacent to the tunneling-layer, and a second charge-storage layer overlying the first charge-storage layer, wherein the first charge-storage layer is separated from the second charge-storage layer by a thin anti-tunneling layer comprising an oxide; depositing a positive charge on the uppermost surface of the charge-storage-layer and determining a positive tunneling voltage for the structure; depositing a negative charge on the uppermost surface of the charge-storage-layer and determining a negative tunneling voltage for the structure; determining a differential tunneling voltage by calculating a difference between the positive and negative tunneling voltages, wherein forming the structure comprises removing a blocking-dielectric-layer comprising a high K dielectric overlying the charge-storage-layer. ### Claim 7 A method comprising: forming on a substrate a test structure including a tunneling-layer comprising a nitrided oxide and a charge-storage-layer overlying the tunneling-layer, the charge-storage-layer comprising a first charge-storage layer adjacent to the tunneling-layer, and a second charge-storage layer overlying the first charge-storage layer, wherein the first charge-storage layer is separated from the second charge-storage layer by a thin anti-tunneling layer comprising an oxide; depositing a positive charge on the uppermost surface of the charge-storage-layer and determining a positive tunneling voltage for the structure; depositing a negative charge on the uppermost surface of the charge-storage-layer and determining a negative tunneling voltage for the structure; determining a differential tunneling voltage by calculating a difference between the positive and negative tunneling voltages; and determining from the differential tunneling voltage an operating characteristic of a non-volatile memory non-volatile memory transistor comprising a charge-storage-layer and a tunneling-layer fabricated concurrently with the charge-storage-layer and tunneling-layer of the structure, wherein forming the structure comprises forming the structure on a monitor substrate processed concurrently with a product substrate on which the non-volatile memory transistor is fabricated. ### Claim 8 A method comprising: forming on a substrate a test structure including a tunneling-layer comprising a nitrided oxide and a charge-storage-layer overlying the tunneling-layer, the charge-storage-layer comprising a first charge-storage layer adjacent to the tunneling-layer, and a second charge- storage layer overlying the first charge-storage layer, wherein the first charge-storage layer is separated from the second charge-storage layer by a thin anti-tunneling layer comprising an oxide; depositing a positive charge on the uppermost surface of the charge-storage-layer and determining a positive tunneling voltage for the structure; depositing a negative charge on the uppermost surface of the charge-storage-layer and determining a negative tunneling voltage for the structure; determining a differential tunneling voltage by calculating a difference between the positive and negative tunneling voltage; and determining from the differential tunneling voltage an operating characteristic of a non-volatile memory transistor comprising a charge-storage-layer and a tunneling-layer fabricated concurrently with the charge-storage-layer and tunneling-layer of the structure; and halting fabrication of non-volatile memory transistors formed concurrently with the structure when the differential tunneling voltage is outside a specified range of voltages. ### Claim 9 (depends on 8) The method of claim 8, wherein the second charge-storage layer comprises a high K dielectric. ### Claim 10 (depends on 8) The method of claim 8, wherein the non-volatile memory transistor further comprises a blocking dielectric layer overlying the charge-storage-layer, wherein the blocking layer comprises a high K dielectric. ### Claim 11 (depends on 8) The method of claim 8, wherein forming the structure comprises forming the structure on a monitor substrate processed concurrently with a product substrate on which the non-volatile memory transistor is fabricated. ### Claim 12 (depends on 11) The method of claim 11, wherein the second charge-storage layer comprises a high K dielectric. ### Claim 13 (depends on 8) The method of claim 8, wherein forming the structure comprises forming the structure on a product substrate on which the non-volatile memory transistor is fabricated. ### Claim 14 A method comprising: forming a structure including a charge-storage-layer overlying a tunneling-layer on a substrate; depositing a positive charge at a first site on the uppermost surface of the charge-storage-layer and determining a first voltage to establish a first leakage current through the charge-storage-layer and the tunneling-layer; depositing a negative charge at a second site on the uppermost surface of the charge-storage-layer and determining a second voltage to establish a second leakage current through the charge-storage-layer and the tunneling-layer; and determining a differential voltage by calculating a difference between the first and second voltages, wherein forming the structure comprises removing a blocking-dielectric-layer comprising a high K dielectric overlying the charge-storage-layer. ### Claim 15 (depends on 14) The method of claim 14, wherein forming the charge-storage-layer comprises a first charge-storage layer adjacent to the tunneling-layer, and a second charge-storage layer overlying the first charge-storage layer. ### Claim 16 (depends on 15) The method of claim 15, wherein the first charge-storage layer is separated from the second charge-storage layer by a thin anti-tunneling layer comprising an oxide. ### Claim 17 (depends on 14) The method of claim 14, wherein forming the tunneling-layer comprises forming a tunneling-layer comprising a nitrided oxide.