# US 8,771,905 B2 · Exposure mask and method for manufacturing same and method for manufacturing semiconductor device

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- Number: US 8,771,905 B2
- Document ID: US8771905B2
- Status: Granted
- Kind: B2
- Application number: 13/491,641
- Filed: 2012-06-08
- Published: 2012-09-27
- Granted: 2014-07-08
- Earliest claimed: 2009-02-06
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Masamitsu Itoh
- Inventors: Masamitsu Itoh
- Web page: https://patentgrep.com/patent/US8771905B2

## CPC

- G03F 1/24: Reflection masks; Preparation thereof
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- B82Y 40/00: Manufacture or treatment of nanostructures
- G03F 1/40: Electrostatic discharge [ESD] related features, e.g. antistatic coatings or a conductive metal layer around the periphery of the mask substrate
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

An exposure mask includes: an insulative substrate; a light reflecting film provided on the substrate; a light absorbing film provided on the light reflecting film and forming a pattern in a center region on the substrate; and an interconnect provided on the substrate, the light reflecting film and the light absorbing film not being provided in a frame-shaped region surrounding the center region, and the interconnect being placed so that a portion of a laminated film composed of the light reflecting film and the light absorbing film located inside the frame-shaped region is electrically connected to a portion of the laminated film located outside the frame-shaped region.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, comprising:
forming a resist film on a semiconductor substrate;
exposing the resist film using an exposure mask;
developing the resist film to form a resist pattern; and
using the resist pattern as a mask to selectively process the semiconductor substrate,
the exposure mask including:
an insulative substrate having a main surface, the main surface including:
a center region;
an intermediate region surrounding the center region; and
an outer region surrounding the intermediate region;
a light reflecting film provided on the center region and the outer region;
a light absorbing film provided on the light reflecting film and forming a pattern in the center region; and
an interconnect provided across the intermediate region and electrically connecting a portion of a laminated film, composed of the light reflecting film and the light absorbing film, located in the center region and a portion of the laminated film located in the outer region, a width of the interconnect being smaller than a minimum width of the pattern,
wherein the light reflecting film and the light absorbing film are not provided in the intermediate region.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the portion of the laminated film located outside the intermediate region and an outer peripheral portion of the intermediate region are shielded from light during the exposing.

### Claim 3 (depends on 1)

The method according to claim 1, wherein a width of the interconnect is such that an image of the interconnect is not imaged when exposure light reflected by the interconnect reaches the resist film.