Semiconductor device and method for manufacturing semiconductor device
AssigneeFuji Electric Co., Ltd.
InventorsMichio Nemoto, Takashi Yoshimura
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AssigneeFuji Electric Co., Ltd.
InventorsMichio Nemoto, Takashi Yoshimura
Estimating the term…
A p anode layer (2) is formed on one main surface of an n− drift layer (1). An n+ cathode layer (3) having an impurity concentration more than that of the n− drift layer (1) is formed on the other main surface of the n− drift layer (1). An anode electrode (4) is formed on the surface of the p anode layer (2). A cathode electrode (5) is formed on the surface of the n+ cathode layer (3). An n-type broad buffer region (6) that has a net doping concentration more than the bulk impurity concentration of a wafer and less than that of the n+ cathode layer (3) and the p anode layer (2) is formed in the n− drift layer (1). The resistivity ρ0 of the n− drift layer (1) satisfies 0.12V0≦ρ0≦0.25V0 with respect to a rated voltage V0. The total amount of the net doping concentration of the broad buffer region (6) is equal to or more than 4.8×1011 atoms/cm2 and equal to or less than 1.0×1012 atoms/cm2.
A semiconductor device comprising:
A semiconductor device comprising:
A method of manufacturing a semiconductor device including a first first-conductivity-type semiconductor layer, a second second-conductivity-type semiconductor layer that is provided on one main surface of the first semiconductor layer and has an impurity concentration more than that of the first semiconductor layer, a third first-conductivity-type semiconductor layer that is provided on the other main surface of the first semiconductor layer and has an impurity concentration more than that of the first semiconductor layer, and a first-conductivity-type broad buffer region that is provided in the first semiconductor layer and has an impurity concentration more than that of the first semiconductor layer and in which a local maximum value of an impurity concentration distribution is less than the impurity concentration of the second semiconductor layer and the third semiconductor layer, comprising:
A method of manufacturing a semiconductor device including a first first-conductivity-type semiconductor layer, a second second-conductivity-type semiconductor layer that is provided on one main surface of the first semiconductor layer and has an impurity concentration more than that of the first semiconductor layer, a third first-conductivity-type semiconductor layer that is provided on the other main surface of the first semiconductor layer and has an impurity concentration more than that of the first semiconductor layer, and a first-conductivity-type broad buffer region that is provided in the first semiconductor layer and has an impurity concentration more than that of the first semiconductor layer and in which a local maximum value of an impurity concentration distribution is less than the impurity concentration of the second semiconductor layer and the third semiconductor layer, comprising:
Dependencies are inferred from the claim text.