Selectively scheduling memory accesses in parallel based on access speeds of memory

An apparatus, comprising:

• determination logic implemented in hardware and configured to determine arithmetic modulo results associated with addresses of a plurality of page requests on a per page request basis, wherein each of the arithmetic modulo result is based, at least in part, on a modulus, wherein the determination logic is configured to use the arithmetic modulo results to determine corresponding access speeds of the plurality of page requests, wherein the access speeds are a number of clock cycles to access memory pages associated with the plurality of page requests,
• wherein the plurality of page requests are addressed to the memory pages in a memory device that is comprised of multiple level memory cells with a same bit density, and wherein the multiple level cells store two or more bits, wherein the plurality of page requests are requests to the memory pages of the memory device, wherein the modulus is based, at least in part, on access speeds of the memory pages, wherein at least two of the plurality of page requests are requesting access to a sequential string of memory pages on a per page request basis,
• wherein the memory pages include a first set of memory pages that are accessed according to a first access speed and a second set of memory pages that are accessed according to a second access speed that is different from the first access speed;
• and
• controller logic configured to schedule two or more page requests from the plurality of page requests to access the memory pages in parallel when memory pages associated with the two or more page requests have a same access speed, wherein the controller logic is configured to schedule the two or more page requests to be serviced in parallel in a same number of clock cycles by aligning the two or more page requests to be executed in parallel.

A method, comprising:

• receiving, in a hardware controller, a plurality of memory requests;
• determining an arithmetic modulo result for each of the plurality of memory requests, wherein the arithmetic modulo result is based, at least in part, on an address of each of the plurality of memory requests and a modulus;
• determining access speeds for the plurality of page requests, wherein an access speed for each of the plurality of page requests is a number of clock cycles to access a memory page associated with each of the plurality of page requests;
• selecting memory requests from the plurality of memory requests that are to be processed by a memory device comprised of multiple level memory cells with a same bit density, wherein the plurality of page requests are requests to access memory pages mapped to the memory device, wherein the multiple level cells include a first set of memory pages that are accessed according to a first access speed and a second set of memory pages that are accessed according to a second access speed that is different from the first access speed, wherein the selected memory requests are requesting to access a sequential string of memory pages on a per page request basis, wherein the modulus is based, at least in part, on access speeds of the sequential string of memory pages, and wherein selecting the memory requests is based, at least in part, on the access speeds;
• issuing the selected memory requests to be processed in parallel by the memory device, wherein the selected memory requests have a same access speed, wherein issuing the selected memory requests includes aligning the selected memory requests,
• wherein issuing the selected memory requests includes controlling the selected memory requests to be executed in parallel, and wherein selecting each of the memory requests is based, at least in part, on the arithmetic modulo result.