# US 8,751,997 B1 · Processing a fast speed grade circuit design for use on a slower speed grade integrated circuit

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- Number: US 8,751,997 B1
- Document ID: US8751997B1
- Status: Granted
- Kind: B1
- Application number: 13/804,774
- Filed: 2013-03-14
- Granted: 2014-06-10
- Earliest claimed: 2013-03-14
- Assignees: Xilinx, Inc.
- Applicants: Xilinx, Inc.
- Inventors: Amit Gupta
- Web page: https://patentgrep.com/patent/US8751997B1

## CPC

- G06F 30/343: Logical level
- G06F 30/3312: Timing analysis
- G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F 2119/12: Timing analysis or timing optimisation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Up-binning a circuit design includes receiving a first bitstream specifying the circuit design. The circuit design meets a timing requirement for a first speed grade of a programmable integrated circuit. Using a processor, a first parameter of the first bitstream is determined. The first parameter is applied to a hardware netlist of the programmable integrated circuit resulting in a parameterized hardware netlist specifying the circuit design. A timing analysis is performed upon the parameterized hardware netlist. The process further includes determining, from the timing analysis, whether at least a portion of the parameterized hardware netlist meets the timing requirement when using timing data for a second speed grade of the programmable integrated circuit. The second speed grade is slower than the first speed grade.

## Claims

### Claim 1

A method, comprising:
receiving a first bitstream specifying a circuit design;
wherein the circuit design meets a timing requirement for a first speed grade of a programmable integrated circuit;
determining, using a processor, a first parameter of the first bitstream;
applying the first parameter to a hardware netlist of the programmable integrated circuit resulting in a parameterized hardware netlist specifying the circuit design;
performing a timing analysis upon the parameterized hardware netlist; and
determining, from the timing analysis, whether at least a portion of the parameterized hardware netlist meets the timing requirement when using timing data for a second speed grade of the programmable integrated circuit;
wherein the second speed grade is slower than the first speed grade.

### Claim 2 (depends on 1)

The method of claim 1, wherein the timing data for the second speed grade of the programmable integrated circuit comprises silicon characterization data.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
modifying the circuit design to meet the timing requirement using the timing data specific to the circuit design for the second speed grade of the programmable integrated circuit.

### Claim 4 (depends on 3)

The method of claim 3, wherein modifying the circuit design comprises:
generating a software model of the circuit design from the parameterized hardware netlist; and
generating a software timing model from timing data generated from the timing analysis of the parameterized hardware netlist.

### Claim 5 (depends on 4)

The method of claim 4, further comprising:
generating a second bitstream from the software model.

### Claim 6 (depends on 5)

The method of claim 5, wherein the second bitstream is functionally equivalent to the first bitstream.

### Claim 7 (depends on 5)

The method of claim 5, further comprising:
extracting a second parameter from the second bitstream;
applying the second parameter to the hardware netlist of the programmable integrated circuit resulting in a second parameterized hardware netlist specifying the circuit design; and
determining whether at least a portion of the second parameterized hardware netlist meets the timing requirement when using the timing data specific to the circuit design for a second programmable integrated circuit of a same type as the first programmable integrated circuit.

### Claim 8 (depends on 5)

The method of claim 5, further comprising:
comparing the first bitstream with the second bitstream; and
indicating whether the second bitstream is functionally equivalent to the first bitstream.

### Claim 9

A system, comprising:
a processor programmed to initiate executable operations comprising:
receiving a first bitstream specifying a circuit design;
wherein the circuit design meets a timing requirement for a first speed grade of a programmable integrated circuit;
determining a first parameter of the first bitstream;
applying the first parameter to a hardware netlist of the programmable integrated circuit resulting in a parameterized hardware netlist specifying the circuit design;
performing a timing analysis upon the parameterized hardware netlist; and
determining, from the timing analysis, whether at least a portion of the parameterized hardware netlist meets the timing requirement when using timing data for a second speed grade of the programmable integrated circuit;
wherein the second speed grade is slower than the first speed grade.

### Claim 10 (depends on 9)

The system of claim 9, wherein the timing data for the second speed grade of the programmable integrated circuit comprises silicon characterization data.

### Claim 11 (depends on 9)

The system of claim 9, wherein the processor is further programmed to initiate an executable operation comprising:
modifying the circuit design to meet the timing requirement using the timing data specific to the circuit design for the second speed grade of the programmable integrated circuit.

### Claim 12 (depends on 11)

The system of claim 11, wherein modifying the circuit design comprises:
generating a software model of the circuit design from the parameterized hardware netlist; and
generating a software timing model from timing data generated from the timing analysis of the parameterized hardware netlist.

### Claim 13 (depends on 11)

The system of claim 11, wherein the processor is further programmed to initiate an executable operation comprising:
generating a second bitstream from the software model.

### Claim 14 (depends on 13)

The system of claim 13, wherein the second bitstream is functionally equivalent to the first bitstream.

### Claim 15 (depends on 14)

The system of claim 14, wherein the processor is further programmed to initiate executable operations comprising:
extracting a second parameter from the second bitstream;
applying the second parameter to the hardware netlist of the programmable integrated circuit resulting in a second parameterized hardware netlist specifying the circuit design; and
determining whether at least a portion of the second parameterized hardware netlist meets the timing requirement when using the timing data specific to the circuit design for a second programmable integrated circuit of a same type as the first programmable integrated circuit.

### Claim 16 (depends on 13)

The system of claim 13, wherein the processor is further programmed to initiate executable operations comprising:
comparing the first bitstream with the second bitstream; and
indicating whether the second bitstream is functionally equivalent to the first bitstream.

### Claim 17

A non-transitory computer-readable medium having instructions stored thereon that, when executed by a processor, cause the processor to perform a method comprising:
receiving a first bitstream specifying a circuit design;
wherein the circuit design meets a timing requirement for a first speed grade of a programmable integrated circuit;
determining, using a processor, a first parameter of the first bitstream;
applying the first parameter to a hardware netlist of the programmable integrated circuit resulting in a parameterized hardware netlist specifying the circuit design;
performing a timing analysis upon the parameterized hardware netlist; and
determining, from the timing analysis, whether at least a portion of the parameterized hardware netlist meets the timing requirement when using timing data for a second speed grade of the programmable integrated circuit;
wherein the second speed grade is slower than the first speed grade.

### Claim 18 (depends on 17)

The non-transitory computer-readable medium of claim 17, wherein the timing data for the second speed grade of the programmable integrated circuit comprises silicon characterization data.

### Claim 19 (depends on 17)

The non-transitory computer-readable medium of claim 17, wherein the method further comprises:
modifying the circuit design to meet the timing requirement using the timing data specific to the circuit design for the second speed grade of the programmable integrated circuit by generating a software model from the parameterized hardware netlist and a software timing model from timing data generated from the timing analysis of the parameterized hardware netlist.

### Claim 20 (depends on 19)

The non-transitory computer-readable medium of claim 19, wherein the method further comprises:
generating a second bitstream from the software model;
wherein the second bitstream is functionally equivalent to the first bitstream.