# US 8,751,994 B2 · System and method for testing stacked dies

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- Number: US 8,751,994 B2
- Document ID: US8751994B2
- Status: Granted
- Kind: B2
- Application number: 14/020,918
- Filed: 2013-09-09
- Published: 2014-01-16
- Granted: 2014-06-10
- Earliest claimed: 2012-07-11
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Sandeep Kumar Goel
- Web page: https://patentgrep.com/patent/US8751994B2

## CPC

- H03K 5/04: by increasing duration; by decreasing duration
- G06F 30/343: Logical level
- G06F 30/394: Routing (G06F30/396 takes precedence)
- G06F 30/396: Clock trees
- G11C 29/26: Accessing multiple arrays (G11C29/24 takes precedence)
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 29/50012: {of timing}
- G06F 12/00: Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06)
- G06F 13/4004: {Coupling between buses}
- G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G11B 19/04: Arrangements for preventing, inhibiting, or warning against double recording on the same blank or against other recording or reproducing malfunctions
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
- G11C 11/4063: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C 11/419: Read-write [R-W] circuits
- G11C 16/32: Timing circuits
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G11B: INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER (recording measured values in a way that does not require playback through a transducer G01D9/00; recording or playback apparatus using mechanically marked tape, e.g. punched paper tape, or using unit records, e.g. punched or magnetically marked cards G06K; transferring data from one type of record carrier to another G06K1/18; circuits for coupling output of reproducer to radio receiver H04B1/20; gramophone pick-ups or like acoustic electromechanical transducers or circuits therefor H04R)

## Abstract

Systems and methods are disclosed for testing dies in a stack of dies and inserting a repair circuit which, when enabled, compensates for a delay defect in the die stack. Intra-die and inter-die slack values are determined to establish which die or dies in the die stack would benefit from the insertion of a repair circuit.

## Claims

### Claim 1

A method for compensating for a delay defect in a die stack, the method comprising the steps of:
(a) determining a first slack value for a first inter-die path between a first and a second die in the die stack;
(b) determining a second slack value for a second inter-die path between the first and second dies;
(c) comparing the first slack value to the second slack value; and
(d) delaying a clock signal to a data storage circuit in the first die by a predetermined amount via a repair circuit in the first die.

### Claim 2 (depends on 1)

The method of claim 1 wherein the predetermined amount of delay is programmable.

### Claim 3 (depends on 1)

The method of claim 1 wherein the predetermined amount of delay is selectable.

### Claim 4 (depends on 1)

The method of claim 1 wherein the predetermined amount is less than or equal to the smaller of the first and second slack values.

### Claim 5 (depends on 1)

The method of claim 1 wherein the first die operates in a first clock domain and the second die operates in a second clock domain.

### Claim 6 (depends on 1)

The method of claim 1 wherein the data storage circuit is a scan flip-flop circuit which sends a data signal from the first die to the second die.

### Claim 7

A method for testing a die stack, the method comprising the steps of:
(a) determining a first slack value for a first inter-die path between the first die and a second die in the die stack;
(b) determining a second slack value for a second inter-die path between the first and second dies; and
(c) inserting a repair circuit in the first die if both the first slack value and the second slack value are greater than a predetermined value.

### Claim 8 (depends on 7)

The method of claim 7 further comprising the step of:
(d) enabling the repair circuit so as to delay a clock signal to a data storage circuit in the first die by a predetermined amount corresponding to the predetermined value.

### Claim 9 (depends on 8)

The method of claim 8 wherein the data storage circuit is a scan flip-flop circuit which sends a data signal from the first die to the second die.

### Claim 10 (depends on 7)

The method of claim 7 wherein the predetermined amount of delay is programmable.

### Claim 11 (depends on 7)

The method of claim 7 wherein the predetermined amount of delay is selectable.

### Claim 12 (depends on 7)

The method of claim 7 wherein the predetermined amount is less than or equal to the smaller of the first and second slack values.

### Claim 13 (depends on 7)

The method of claim 7 wherein the first die operates in a first clock domain and the second die operates in a second clock domain.

### Claim 14

A system comprising:
a first die comprising:
a first data storage circuit; and
a repair circuit connected to the first data storage circuit;
and
a second die connected to the first die, the second die comprising:
a second data storage circuit;
a first inter-die path connecting the first data storage circuit to the second data storage circuit, the first inter-die path having a first path slack value and
a second inter-die path connecting said first data storage circuit to said second data storage circuit, said second path having a second path slack value,
wherein the repair circuit conditionally delays a clock signal to the first data storage circuit by a predetermined amount.

### Claim 15 (depends on 14)

The system of claim 14, the first die further comprising an intra-die path for passing information to the first data storage circuit, the intra-die path having an intra-die slack value, and wherein the intra-die path has a known defect value.

### Claim 16 (depends on 15)

The system of claim 15, wherein the repair circuit delays the clock signal to the first data storage circuit if the known defect value is greater than the intra-die path slack value and if the known defect value is less than or equal to the first path slack value or the second path slack value.

### Claim 17 (depends on 14)

The system of claim 14, the first die further comprising an intra-die path for passing information to the first data storage circuit, the intra-die path having an intra-die slack value.

### Claim 18 (depends on 17)

The system of claim 17, wherein the repair circuit delays the clock signal if both the first slack value and the second slack value are greater than the intra-die slack value.

### Claim 19 (depends on 14)

The system of claim 14 wherein the first die operates in a first clock domain and the second die operates in a second clock domain.

### Claim 20 (depends on 14)

The system of claim 14 wherein the data storage circuit is a scan flip-flop circuit which sends a data signal from the first die to the second die.