# US 8,751,991 B2 · Layout method, layout system, and non-transitory computer readable medium storing layout program of semiconductor integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,751,991 B2 - Document ID: US8751991B2 - Status: Granted - Kind: B2 - Application number: 13/099,658 - Filed: 2011-05-03 - Published: 2011-11-17 - Granted: 2014-06-10 - Earliest claimed: 2010-05-13 - Assignees: Renesas Electronics Corporation - Applicants: Kazuyuki Irie - Inventors: Kazuyuki Irie - Web page: https://patentgrep.com/patent/US8751991B2 ## CPC - G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A layout method of a semiconductor integrated circuit according to the present invention includes selecting M (M is an integer of two or larger and N or smaller) pieces of sequential circuits from N (N is an integer of three or larger) pieces of sequential circuits mounted on the semiconductor integrated circuit, a clock being distributed to the N pieces of sequential circuits from the same clock route; and replacing the M pieces of sequential circuits that are selected with one multi-data input/output sequential circuit including M pieces of input terminals and output terminals and one clock terminal that receives the clock distributed from the clock route. ## Claims ### Claim 1 A layout method of a semiconductor integrated circuit, comprising: selecting, via a processor, M (M is an integer of two or larger and N or smaller) pieces of sequential circuits from N (N is an integer of three or larger) pieces of sequential circuits mounted on the semiconductor integrated circuit, a clock being distributed to the N pieces of sequential circuits from a same clock route; and replacing the M pieces of sequential circuits that are selected with a single multi-data input/output sequential circuit, having a single flip-flop, including M pieces of input terminals and output terminals and a single clock terminal that receives the clock distributed from the clock route. ### Claim 2 (depends on 1) The layout method according to claim 1, comprising: executing timing verification when it is assumed that replacement is performed with the multi-data input/output sequential circuit for a former-stage path and a latter-stage path of each of the M pieces of sequential circuits that are selected using arrangement information of the M pieces of sequential circuits that are selected and arrangement information of the multi-data input/output sequential circuit when it is assumed that the replacement is performed; and performing replacement with the multi-data input/output sequential circuit when there is no timing error in all the former-stage paths and the latter-stage paths in which the timing verification is executed. ### Claim 3 (depends on 2) The layout method according to claim 2, comprising executing the timing verification for the former-stage path and the latter-stage path of each of the M pieces of sequential circuits that are selected further using a clock skew value after Clock Tree Synthesis (CTS) is executed. ### Claim 4 (depends on 2) The layout method according to claim 2, comprising executing the timing verification for the former-stage path and the latter-stage path of each of the M pieces of sequential circuits that are selected further using an On Chip Variation (OCV) value of a clock. ### Claim 5 (depends on 2) The layout method according to claim 2, comprising: executing timing analysis for the N pieces of sequential circuits; selecting a part or all of the sequential circuits in which timing error is occurred as the M pieces of sequential circuits; and replacing the M pieces of sequential circuits that are selected with the one multi-data input/output sequential circuit. ### Claim 6 (depends on 2) The layout method according to claim 2, comprising: selecting the M pieces of sequential circuits from the N pieces of sequential circuits before Clock Tree Synthesis (CTS) is executed; replacing the M pieces of sequential circuits that are selected with the one multi-data input/output sequential circuit; executing CTS based on arrangement information after the replacement; selecting a plurality of sequential circuits from a sequential circuit which is not replaced among the N pieces of sequential circuits and the multi-data input/output sequential circuit which is replaced after the CTS is executed; and replacing the plurality of sequential circuits that are selected with the one multi-data input/output sequential circuit in consideration of a clock skew value after the CTS is executed. ### Claim 7 (depends on 3) The layout method according to claim 3, comprising: calculating a clock skew value after executing CTS; selecting a part or all of the sequential circuits corresponding to a path in which the clock skew value exceeds a predetermined value as the M pieces of sequential circuits; and replacing the M pieces of sequential circuits that are selected with the one multi-data input/output sequential circuit. ### Claim 8 (depends on 3) The layout method according to claim 3, comprising: executing timing analysis for the N pieces of sequential circuits; selecting a part or all of the sequential circuits in which timing error is occurred as the M pieces of sequential circuits; and replacing the M pieces of sequential circuits that are selected with the one multi-data input/output sequential circuit. ### Claim 9 (depends on 1) The layout method according to claim 1, comprising: executing timing analysis for the N pieces of sequential circuits; selecting a part or all of the sequential circuits in which timing error is occurred as the M pieces of sequential circuits; and replacing the M pieces of sequential circuits that are selected with the one multi-data input/output sequential circuit. ### Claim 10 (depends on 1) The layout method according to claim 1, comprising: selecting the M pieces of sequential circuits from the N pieces of sequential circuits before Clock Tree Synthesis (CTS) is executed; replacing the M pieces of sequential circuits that are selected with the one multi-data input/output sequential circuit; executing CTS based on arrangement information after the replacement; selecting a plurality of sequential circuits from a sequential circuit which is not replaced among the N pieces of sequential circuits and the multi-data input/output sequential circuit after replacement after the CTS is executed; and replacing the plurality of sequential circuits that are selected with the one multi-data input/output sequential circuit in consideration of a clock skew value after the CTS is executed. ### Claim 11 (depends on 1) The layout method according to claim 1, wherein the single flip-flop is a multi-bit flip-flop. ### Claim 12 A layout system of a semiconductor integrated circuit using a computer, the computer comprising: a storage unit configured to store arrangement information of N (N is an integer of three or larger) pieces of sequential circuits mounted on the semiconductor integrated circuit, a clock being distributed to the N pieces of sequential circuits from a same clock route; and a control unit configured to execute layout of the sequential circuits in the semiconductor integrated circuit, wherein the control unit comprises: a selection unit configured to select M (M is an integer of two or larger and N or smaller) pieces of sequential circuits from the N pieces of sequential circuits; and a replacement unit configured to replace the M pieces of sequential circuits that are selected with a single multi-data input/output sequential circuit, having a single flip-flop, including M pieces of input terminals and output terminals and a single clock terminal that receives a clock distributed from the clock route. ### Claim 13 (depends on 12) The layout system according to claim 12, wherein the control unit further comprises a timing verification unit configured to execute timing verification when it is assumed that replacement is performed with the multi-data input/output sequential circuit for a former-stage path and a latter-stage path of each of the M pieces of sequential circuits that are selected using arrangement information of the M pieces of sequential circuits that are selected and arrangement information of the multi-data input/output sequential circuit when it is assumed that the replacement is performed, and the replacement unit is configured to perform replacement with the multi-data input/output sequential circuit when there is no timing error in all the former-stage paths and the latter-stage paths in which the timing verification is executed. ### Claim 14 (depends on 13) The layout system according to claim 13, wherein the timing verification unit executes the timing verification for the former-stage path and the latter-stage path of each of the M pieces of sequential circuits that are selected further using a clock skew value after Clock Tree Synthesis (CTS) is executed. ### Claim 15 (depends on 14) The layout system according to claim 14, wherein the control unit further comprises a calculation unit configured to calculate a clock skew value after Clock Tree Synthesis (CTS) is executed, the selection unit configured to select a part or all of the sequential circuits corresponding to a path in which the clock skew value exceeds a predetermined value as the M pieces of sequential circuits, and the replacement unit configured to replace the M pieces of sequential circuits that are selected with the one multi-data input/output sequential circuit. ### Claim 16 (depends on 12) The layout system according to claim 12, wherein the control unit further comprises a timing analysis unit configured to execute timing analysis for the N pieces of sequential circuits, the selection unit configured to select a part or all of the sequential circuits in which timing error is occurred as the M pieces of sequential circuits, and the replacement unit configured to replace the M pieces of sequential circuits that arc selected with the one multi-data input/output sequential circuit. ### Claim 17 (depends on 12) The layout system according to claim 12, wherein the single flip-flop is a multi-bit flip-flop. ### Claim 18 A non-transitory computer readable medium storing a layout program of a semiconductor integrated circuit that makes a computer execute processing including: selection processing that selects M (M is an integer of two or larger and N or smaller) pieces of sequential circuits from N (N is an integer of three or larger) pieces of sequential circuits mounted on the semiconductor integrated circuit, a clock being distributed to the N pieces of sequential circuits from a same clock route; and replacement processing that replaces the M pieces of sequential circuits that are selected with a single multi-data input/output sequential circuit, having a single flip-flop, including M pieces of input terminals and output terminals and a single clock terminal that receives the clock distributed from the clock route. ### Claim 19 (depends on 18) The non-transitory computer readable medium storing the layout program according to claim 18, further comprising: timing verification processing that executes timing verification when it is assumed that replacement is performed with the multi-data input/output sequential circuit for a former-stage path and a latter-stage path of each of the M pieces of sequential circuits that are selected using arrangement information of the M pieces of sequential circuits that are selected and arrangement information of the multi-data input/output sequential circuit when it is assumed that the replacement is performed; wherein the replacement processing performs replacement with the multi-data input/output sequential circuit when there is no timing error in all the former-stage paths and the latter-stage paths in which the timing verification is executed. ### Claim 20 (depends on 19) The non-transitory computer readable medium storing the layout program according to claim 19, wherein the timing verification processing executes the timing verification for the former-stage path and the latter-stage path of each of the M pieces of sequential circuits that are selected further using a clock skew value after Clock Tree Synthesis (CTS) is executed. ### Claim 21 (depends on 20) The non-transitory computer readable medium storing the layout program according to claim 20, further comprising a calculation processing that calculates a clock skew value after the CTS is executed, wherein the selection processing selects a part or all of the sequential circuits corresponding to a path in which the clock skew value exceeds a predetermined value as the M pieces of sequential circuits, and the replacement processing replaces the M pieces of sequential circuits that are selected with the one multi-data input/output sequential circuit. ### Claim 22 (depends on 18) The non-transitory computer readable medium storing the layout program according to claim 18, further comprising timing analysis processing that executes timing analysis for the N pieces of sequential circuits; wherein the selection processing selects a part or all of the sequential circuits in which timing error is occurred by the timing analysis processing as the M pieces of sequential circuits, and the replacement processing replaces the M pieces of sequential circuits that are selected with the one multi-data input/output sequential circuit. ### Claim 23 (depends on 18) The non-transitory computer readable medium storing the layout program according to claim 18, wherein the single flip-flop is a multi-bit flip-flop.