# US 8,751,983 B1 · Method for design partitioning at the behavioral circuit design level

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- Number: US 8,751,983 B1
- Document ID: US8751983B1
- Status: Granted
- Kind: B1
- Application number: 13/789,192
- Filed: 2013-03-07
- Granted: 2014-06-10
- Earliest claimed: 2013-03-07
- Assignees: Oracle International Corporation
- Applicants: Oracle International Corporation
- Inventors: Thomas Mitchell; Krishnan Sundaresan; Quan Tran; Yibin Xia
- Web page: https://patentgrep.com/patent/US8751983B1

## CPC

- G06F 30/30: Circuit design
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A design partitioning method and apparatus includes an RTL reader module configured to receive, process, and parse hardware descriptive language of a circuit design; an expression graph module configured to trace identified signal dependencies to determine dependent elements along selected paths within the circuit design; a hierarchy flattener module configured to remove existing circuit design hierarchies based on the identified signal dependencies and determined dependent elements; a partition specification reader module that defines selected paths within the circuit design into a partition specification; a design partitioner module configured to separate the flattened circuit design hierarchy according to the partition specification; a re-partitioner module configured to create a second hierarchical circuit design structure based on the separated, flattened circuit design hierarchy that is behaviorally identical to the circuit design; and an RTL design write-out module configured to output the second hierarchical circuit design structure for analysis.

## Claims

### Claim 1

A method for performing design partitioning at the behavioral circuit design level comprising:
receiving, processing, and parsing hardware descriptive language of a circuit design;
tracing identified signal dependencies to determine dependent elements along selected paths within the circuit design;
removing existing circuit design hierarchies based on the identified signal dependencies and determined dependent elements;
defining selected paths within the circuit design;
wherein the selected paths are traced from inputs to outputs according to a partition specification;
separating a flattened circuit design hierarchy according to the partition specification;
creating a second hierarchical circuit design structure based on the separated, flattened circuit design hierarchy that is behaviorally identical to the hardware descriptive language of the circuit design; and
outputting the second hierarchical circuit design structure for analysis.

### Claim 2 (depends on 1)

The method of claim 1, wherein the method is performed in selected modes comprising:
single-threaded or multi-threaded execution modes;
execution by a CPU, a GPU, other processor, or any combination thereof;
execution in serial processing mode, in parallel processing mode, or in combination thereof; and
execution in partitioning mode or in input duplicating mode.

### Claim 3 (depends on 1)

The method of claim 1 further comprising:
receiving and processing register transfer level (RTL) code representing the circuit design is performed separately from parsing the behavioral representation of the circuit design to identify signal dependencies within the circuit design.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
accepting a hardware description language input model and operating on a register-transfer-level (RTL) or network of nodes;
receiving analog, digital, or mixed analog-and-digital RTL representations;
accepting combinational, sequential, or mixed combinational-and-sequential networks;
operating on a synchronous, asynchronous, or mixed synchronous-and-asynchronous networks;
accepting a single or a plurality of HDL files containing RTL circuit design information;
receiving RTL circuit design information from a character scanner; and
operating on the RTL circuit design information provided by dedicated input files or from a database.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
performing the trace of the signal dependencies separately from performing the trace of the selected paths.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
translating the hardware description language (HDL) according to a set of predefined rules;
translating the hardware description language into an array of program variables; and
representing the hardware description language in a graphic-equivalent software model.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
operating on a single portion thereof, a plurality of portions thereof, or on all of the circuit design.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
accepting partition specification containing input and output circuit design nodes;
accepting partition specification containing instances of circuit design modules;
operating on a single partition specification or a plurality of partition specifications;
receiving partition specification from input files or a database; and
accepting partition specification from a character scanner.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
writing the RTL output into a single output or in a plurality of outputs;
writing the RTL output into data files or as a data streams to a database;
displaying the design write-out on a visual display device;
routing the RTL output to a printed matter device; and
writing the RTL output in distinct coloring and formatting according to a predefined rule or set of rules.

### Claim 10

An apparatus for performing design partitioning at the behavioral circuit design level comprising:
an RTL reader module configured to receive, process, and parse hardware descriptive language of a circuit design;
an expression graph module configured to trace identified signal dependencies to determine dependent elements along selected paths within the circuit design;
a hierarchy flattener module configured to remove existing circuit design hierarchies based on the identified signal dependencies and determined dependent elements to produce a flattened circuit design;
a partition specification reader module that defines selected paths within the circuit design into a partition specification;
wherein the expression graph module traces selected paths from inputs to outputs according to the partition specification;
a design partitioner module configured to separate the flattened circuit design hierarchy according to the partition specification;
a re-partitioner module configured to create a second hierarchical circuit design structure based on the separated, flattened circuit design hierarchy that is behaviorally identical to the hardware descriptive language of the circuit design; and
an RTL design write-out module configured to output the second hierarchical circuit design structure for analysis.

### Claim 11 (depends on 10)

The apparatus of claim 10 further comprising:
an execution sequence order module configured to control an order of execution of individual modules.

### Claim 12 (depends on 10)

The apparatus of claim 10, wherein individual modules are operated in selected modes comprising:
single-threaded or multi-threaded execution modes;
execution by a CPU, a GPU, other processor, or any combination thereof;
execution in serial processing mode, in parallel processing mode, or in combination thereof; and
execution in partitioning mode or in input duplicating mode.

### Claim 13 (depends on 10)

The apparatus of claim 10, wherein the RTL reader module comprises:
a pre-processor module that receives and processes register transfer level (RTL) code representing a circuit design; and
a parser module that parses the behavioral representation of the circuit design to identify signal dependencies within the circuit design.

### Claim 14 (depends on 10)

The apparatus of claim 10, wherein operation of the pre-processor module comprises:
accepting a hardware description language input model and operating on a register-transfer-level (RTL) or network of nodes;
receiving analog, digital, or mixed analog-and-digital RTL representations;
accepting combinational, sequential, or mixed combinational-and-sequential networks;
operating on a synchronous, asynchronous, or mixed synchronous-and-asynchronous networks;
accepting a single or a plurality of hardware description language (HDL) files containing RTL circuit design information;
receiving RTL circuit design information from a character scanner; and
operating on the RTL circuit design information provided by dedicated input files or from a database.

### Claim 15 (depends on 10)

The apparatus of claim 10, wherein the expression graph module comprises:
a first traversal module that performs the trace of the signal dependencies; and
a second traversal module that performs the trace of the selected paths.

### Claim 16 (depends on 10)

The apparatus of claim 10, wherein operation of the expression graph module comprises:
translating the hardware description language (HDL) according to a set of predefined rules;
translating the hardware description language into an array of program variables; and
representing the hardware description language in a graphic-equivalent software model.

### Claim 17 (depends on 10)

The apparatus of claim 10, wherein the hierarchy flattener module is configured to operate on a single portion thereof, a plurality of portions thereof, or on all of the circuit design.

### Claim 18 (depends on 10)

The apparatus of claim 10, wherein the partition specification operation comprises:
accepting partition specification containing input and output circuit design nodes;
accepting partition specification containing instances of circuit design modules;
operating on a single partition specification or a plurality of partition specifications;
receiving partition specification from input files or a database; and
accepting partition specification from a character scanner.

### Claim 19 (depends on 10)

The apparatus of claim 10, wherein the re-partition module is configured to execute a single re-partition, a plurality of re-partitions, or a full re-partition of the circuit design.

### Claim 20 (depends on 10)

The apparatus of claim 10, wherein the RTL design write-out module comprises:
writing the RTL output into a single output or in a plurality of outputs;
writing the RTL output into data files or as data streams to a database;
displaying the design write-out on a visual display device;
routing the RTL output to a printed matter device; and
writing the RTL output in distinct coloring and formatting according to a predefined rule or set of rules.