# US 8,751,982 B2 · Implementing dual speed level shifter with automatic mode control

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- Number: US 8,751,982 B2
- Document ID: US8751982B2
- Status: Granted
- Kind: B2
- Application number: 13/602,164
- Filed: 2012-09-02
- Published: 2012-12-27
- Granted: 2014-06-10
- Earliest claimed: 2011-02-18
- Assignees: International Business Machines Corporation
- Applicants: Joel T. Ficke; David M. Friend; Grant P. Kesselring; James D. Strom; Jianguo Yao
- Inventors: Joel T. Ficke; David M. Friend; Grant P. Kesselring; James D. Strom; Jianguo Yao
- Web page: https://patentgrep.com/patent/US8751982B2

## CPC

- H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00)
- H03L 7/083: the reference signal being additionally directly applied to the generator
- H03L 7/099: concerning mainly the controlled oscillator of the loop
- H03L 7/18: using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected.

## Claims

### Claim 1

A design structure embodied in a non-transitory machine readable medium used in a design process, the design structure comprising:
a circuit tangibly embodied in the non-transitory machine readable medium used in the design process, said circuit for implementing a dual speed level shifter with automatic mode control, said circuit comprising:
a low speed level shifter and a high speed level shifter, each receiving an incoming signal to be level shifted and each having an enable input;
a first counter receiving the incoming signal to be level shifted;
a second counter receiving a reference signal; said first counter and said second counter having an equal size; each of said first counter and said second counter having a respective overflow output; and
a set reset latch (SR) latch receiving a respective set input and reset input of said respective overflow outputs for automatically selecting a low speed mode enabling the low speed level shifter or a high speed mode enabling the high speed level shifter, the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit.

### Claim 2 (depends on 1)

The design structure of claim 1, wherein the design structure comprises a netlist, which describes said circuit.

### Claim 3 (depends on 1)

The design structure of claim 1, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

### Claim 4 (depends on 1)

The design structure of claim 1, wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.

### Claim 5 (depends on 1)

The design structure of claim 1, includes a multiplexer coupled to an output of said low speed level shifter and said high speed level shifter, said mode select output signal applied to a select input of said multiplexer; said multiplexer providing an output from either said low speed level shifter circuit or said high speed level shifter circuit responsive to the mode select output signal.

### Claim 6 (depends on 1)

The design structure of claim 1, includes an OR gate receiving said respective overflow outputs for generating a reset signal; and said reset signal being applied to a respective reset input of said first counter and said second counter.