# US 8,751,977 B2 · Method for generating ultra-short-run-length dummy poly features > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,751,977 B2 - Document ID: US8751977B2 - Status: Granted - Kind: B2 - Application number: 12/949,336 - Filed: 2010-11-18 - Published: 2012-05-24 - Granted: 2014-06-10 - Earliest claimed: 2010-11-18 - Assignees: Texas Instruments Incorporated - Applicants: James Walter Blatchford - Inventors: James Walter Blatchford - Web page: https://patentgrep.com/patent/US8751977B2 ## CPC - G03F 1/36: Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes - G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G) ## Abstract A method and apparatus for designing a lithography mask set which provides polygon features of a desired size at advanced technology nodes, for example, using live features and dummy features. A dummy feature can be formed within a confined space by specifying an allowable dummy feature length even though the feature length may result in contact between the dummy feature and the live feature. After specifying the dummy feature length, a pattern generation (PG) extract can be performed to pull back the dummy feature away from the live feature by an allowable distance. The PG exact process can result in a shorter dummy feature which has a length which is shorter than can be specified directly by design rules, but which passes rule checking. ## Claims ### Claim 1 A method for designing a lithography mask set, comprising: providing a device circuit layout including a first polygon portion having a first orientation and a second polygon portion having a second orientation perpendicular to the first orientation, wherein the second polygon portion forms a line-end geometry; specifying that a separation between the first polygon portion and the second polygon portion is a first distance; specifying that a separation between the second polygon portion and all other polygons in the device circuit layout is at least a second distance that is larger than the first distance; specifying a first length for the second polygon portion; and reducing the length of the second polygon portion from the first length to a second length which is less than the first length, wherein the second length is based on the second feature's proximity to the first feature. ### Claim 2 (depends on 1) The method of claim 1, further comprising: providing a third polygon portion having the second orientation and separated from all other polygons in the device circuit layout by a third distance that is larger than the first distance; and specifying that the third polygon portion has a third length that is at least as long as the first length. ### Claim 3 (depends on 2) The method of claim 2, further comprising: specifying that the first distance is equal to zero such that the first length results in electrical contact between the second polygon portion and the first polygon portion; specifying that the third distance is at least as large as the second distance; and subsequent to specifying that the third polygon portion has the third length, performing a pattern generation (PG) extract process on the device circuit layout such that, subsequent to performing the PG extract process, the second polygon portion has the second length which is less than both the first length and the third length and the second polygon portion is spaced from first polygon portion by a distance greater than zero. ### Claim 4 (depends on 1) The method of claim 1, further comprising: specifying that the first distance is less than or equal to 0.9 times the second distance. ### Claim 5 (depends on 1) The method of claim 1, further comprising: specifying that the second length is less than or equal to 0.7 times the first length. ### Claim 6 A computer-readable medium storing a set of instructions which causes a computer system to perform a set of instructions to execute a method comprising: providing a device circuit layout including a first polygon portion having a first orientation and a second polygon portion having a second orientation perpendicular to the first orientation, wherein the second polygon portion forms a line-end geometry; specifying that a separation between the first polygon portion and the second polygon portion is equal to a first distance; specifying that a separation between the second polygon portion and all other polygons in the device circuit layout is at least a second distance that is larger than the first distance; specifying a first length for the second polygon portion; and reducing the length of the second polygon portion from the first length to a second length which is less than the first length, wherein the second length is based on the second feature's proximity to the first feature. ### Claim 7 (depends on 6) The computer-readable medium storing the set of instructions of claim 6, wherein the set of instructions further causes a computer system to perform a set of instructions to execute a method further comprising: providing a third polygon portion having the second orientation and separated from all other polygons in the device circuit layout by a third distance that is larger than the first distance; and specifying that the third polygon has a third length that is at least as long as the first length.