# US 8,751,915 B2 · Systems and methods for selectable positive feedback data processing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,751,915 B2 - Document ID: US8751915B2 - Status: Granted - Kind: B2 - Application number: 13/597,001 - Filed: 2012-08-28 - Published: 2014-03-06 - Granted: 2014-06-10 - Earliest claimed: 2012-08-28 - Assignees: LSI Corporation - Applicants: Fan Zhang - Inventors: Fan Zhang - Web page: https://patentgrep.com/patent/US8751915B2 ## CPC - G11B 20/1833: {by adding special lists or symbols to the coded information (G11B20/1806, G11B20/1866 take precedence)} - G11B 20/10268: {bit detection or demodulation methods} - G11B 20/10481: {optimisation methods} - G11B 2020/185: {using an low density parity check [LDPC] code} - G11B 2020/1863: {wherein the Viterbi algorithm is used for decoding the error correcting code} - G11B: INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER (recording measured values in a way that does not require playback through a transducer G01D9/00; recording or playback apparatus using mechanically marked tape, e.g. punched paper tape, or using unit records, e.g. punched or magnetically marked cards G06K; transferring data from one type of record carrier to another G06K1/18; circuits for coupling output of reproducer to radio receiver H04B1/20; gramophone pick-ups or like acoustic electromechanical transducers or circuits therefor H04R) ## Abstract The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for selectable positive feedback data processing. ## Claims ### Claim 1 A data processing system, the data processing system comprising: a data processing circuit operable to re-apply a data processing algorithm to a data set using a processing feedback; a data quality determination circuit operable to indicate a quality of the data set; and an output selector circuit operable to select between a positive feedback and a neutral feedback based at least in part on the quality to yield the processing feedback. ### Claim 2 (depends on 1) The data processing system of claim 1, wherein the data processing circuit comprises: a data detector circuit operable to apply a data detection algorithm to the data set guided by a decoder output to yield the positive feedback; and a summation circuit operable to subtract the decoder output from the positive feedback to yield the neutral feedback. ### Claim 3 (depends on 2) The data processing system of claim 2, wherein the data detector circuit is selected from a group consisting of: a Viterbi algorithm data detector circuit, and a maximum a posteriori data detector circuit. ### Claim 4 (depends on 1) The data processing system of claim 1, wherein the data processing circuit comprises: a data decoder circuit operable to apply a data decode algorithm to the data set guided by a decoder output to yield the positive feedback; and a summation circuit operable to subtract the decoder output from the positive feedback to yield the neutral feedback. ### Claim 5 (depends on 1) The data processing system of claim 1, wherein the data decoder circuit is a low density parity check decoder circuit. ### Claim 6 (depends on 1) The data processing system of claim 1, wherein the quality of the data set corresponds to a number of errors remaining in the data set after application of the data processing algorithm. ### Claim 7 (depends on 6) The data processing system of claim 6, wherein the system further comprises: a comparator circuit operable to compare the quality of the data set with a threshold value, wherein selection between the positive feedback and the neutral feedback is based on a result of the comparison of the quality of the data set with a threshold value. ### Claim 8 (depends on 1) The data processing system of claim 1, wherein the system is implemented as an integrated circuit. ### Claim 9 (depends on 1) The data processing system of claim 1, wherein the system is incorporated in a device selected from a group consisting of: a storage device, and a data transmission device. ### Claim 10 A method for data processing, the method comprising: applying a data decode algorithm by a data decoder circuit to a decoder input derived from a data set guided by an interim decoded output to yield a positive feedback; calculating a quality metric for the data set; subtracting the interim decoded output from the positive feedback to yield a neutral feedback; selecting one of the positive feedback and the neutral feedback as an updated decoded output based at least in part on the quality metric; and re-applying the data decode algorithm to using the updated decoded output. ### Claim 11 (depends on 10) The method of claim 10, wherein the data decoder circuit is a low density parity check decoder circuit. ### Claim 12 (depends on 10) The method of claim 10, the method further comprising: applying a data detection algorithm to the data set guided by the updated decoded output to yield a raw detected output. ### Claim 13 (depends on 12) The method of claim 12, wherein the data detection algorithm is applied by a data detector circuit selected from a group consisting of: a Viterbi algorithm data detector circuit, and a maximum a posteriori data detector circuit. ### Claim 14 (depends on 12) The method of claim 12, wherein the positive feedback is a first positive feedback, wherein the neutral feedback is a first neutral feedback; and wherein the method further comprises: wherein the raw detected output is a second positive feedback; subtracting the updated decoded output from the raw detected output to yield a second neutral feedback; and selecting one of the second positive feedback and the second neutral feedback as an updated detected output based at least in part on the quality metric, wherein the decoder input derived from the updated detected output. ### Claim 15 (depends on 10) The method of claim 10, wherein the method further comprises: comparing the quality metric with a threshold value to yield a comparison value, and wherein the selecting one of the positive feedback and the neutral feedback as the updated decoded output is based on the comparison value. ### Claim 16 (depends on 15) The method of claim 15, the method further comprising: programming the threshold value. ### Claim 17 A storage device, the storage device comprising: a storage medium; a head assembly disposed in relation to the storage medium and operable to provide a sensed signal corresponding to information on the storage medium; a read channel circuit including: an analog to digital converter circuit operable to sample an analog signal derived from the sensed signal to yield a series of digital samples; an equalizer circuit operable to equalize the digital samples to yield a data set; a data processing circuit operable to re-apply a data processing algorithm to the data set using a processing feedback; a data quality determination circuit operable to indicate a quality corresponding to the data set; and an output selector circuit operable to select between a positive feedback and a neutral feedback based at least in part on the quality. ### Claim 18 (depends on 17) The storage device of claim 17, wherein the storage device further comprises: a data detector circuit operable to apply a data detection algorithm to the data set guided by a decoder output to yield the positive feedback; and a summation circuit operable to subtract the decoder output from the positive feedback to yield a neutral feedback. ### Claim 19 (depends on 17) The storage device of claim 17, wherein the storage device further comprises: a data decoder circuit operable to apply a data decode algorithm to a decoder input derived from the data set guided by a decoder output to yield the positive feedback; and a summation circuit operable to subtract the decoder output from the positive feedback to yield a neutral feedback. ### Claim 20 (depends on 19) The storage device of claim 19, wherein the decoder output is a first decoder output, wherein the positive feedback is a first positive feedback and the neutral feedback is a first neutral feedback, and wherein the storage device further comprises: a data detector circuit operable to apply a data detection algorithm to the data set guided by a second decoder output to yield a second positive feedback; and a summation circuit operable to subtract the second decoder output from the second positive feedback to yield a second neutral feedback.