# US 8,751,900 B2 · Storage device having a non-volatile memory device and copy-back method thereof

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- Number: US 8,751,900 B2
- Document ID: US8751900B2
- Status: Granted
- Kind: B2
- Application number: 13/106,892
- Filed: 2011-05-13
- Published: 2011-11-17
- Granted: 2014-06-10
- Earliest claimed: 2010-05-14
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Yong June Kim; Hong Rak Son; Seonghyeog Choi; Junjin Kong; Yongtaew Yim; Jaehong Kim; KyoungLae Cho; Wootae Chang
- Inventors: Yong June Kim; Hong Rak Son; Seonghyeog Choi; Junjin Kong; Yongtaew Yim; Jaehong Kim; KyoungLae Cho; Wootae Chang
- Web page: https://patentgrep.com/patent/US8751900B2

## CPC

- G06F 11/106: {Correcting systematically all correctable errors, i.e. scrubbing}
- H03M 13/1102: {Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes}
- H03M 13/136: {Reed-Muller [RM] codes}
- H03M 13/152: {Bose-Chaudhuri-Hocquenghem [BCH] codes}
- H03M 13/155: {Shortening or extension of codes}
- H03M 13/2909: {Product codes}
- H03M 13/618: {Shortening and extension of codes}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A storage device includes a non-volatile memory device outputting read data from a source area and a memory controller configured to execute an ECC operation on a plurality of vectors in the read data and to write the error-corrected read data into target area of the non-volatile memory device. The memory controller declares that a vector corresponding to a clean area is decoding pass without using a flag bit among the plurality of vectors during the error correction operation.

## Claims

### Claim 1

A storage device comprising:
a non-volatile memory device to output read data from a source area of the non-volatile memory device; and
a memory controller configured to execute an error correction code (ECC) operation on a plurality of vectors in the read data and to write the error-corrected read data into a target area of the non-volatile memory device,
wherein the memory controller determines that a vector corresponding to a unit of non-programmed memory cells among the plurality of vectors is decoding pass without referring to any flag bit indicating a vector programming state among the plurality of vectors during the ECC operation.

### Claim 2 (depends on 1)

The storage device as set forth in claim 1, wherein the read data is page unit data which include a plurality of sectors.

### Claim 3 (depends on 2)

The storage device as set forth in claim 2, wherein the plurality of vectors correspond to the plurality of sectors respectively.

### Claim 4 (depends on 2)

The storage device as set forth in claim 2, wherein the non-volatile memory device writes data in sector units.

### Claim 5 (depends on 1)

The storage device as set forth in claim 1, wherein the memory controller defines an “all one” vector in which each data element is a logical “1” as the vector corresponding to the unit of non-programmed memory cells.

### Claim 6 (depends on 5)

The storage device as set forth in claim 5, wherein the memory controller comprises an ECC unit configured to generate a zero vector syndrome in response to the “all one” vector.

### Claim 7 (depends on 6)

The storage device as set forth in claim 6, wherein, when a length of the vector corresponding to the unit of non-programmed memory cells and a length of a write data unit are different, the ECC unit matches the length of the vector corresponding to the unit of non-programmed memory cells and the write data unit by using a shortening process.

### Claim 8 (depends on 7)

The storage device as set forth in claim 7, wherein the ECC unit regards a shortened part of the unit of non-programmed memory cells as “all one” bits or a symbol corresponding to the “all one” bits during an encoding or decoding operation and discards the shortened one part.

### Claim 9 (depends on 7)

The storage device as set forth in claim 7, wherein the ECC unit executes the ECC operation according to at least one algorithm among binary BCH code, RM code, and RS code.

### Claim 10 (depends on 6)

The storage device as set forth in claim 6, wherein the ECC unit modifies a row weight of a parity check matrix associated with the ECC operation to an even numbered value.

### Claim 11 (depends on 10)

The storage device as set forth in claim 10, wherein the ECC unit executes the ECC operation based on a LDPC algorithm.

### Claim 12 (depends on 6)

The storage device as set forth in claim 6, wherein the ECC unit executes the ECC operation according to a product code associated with at least one of a binary BCH code, a RM code, a RS code and a LDPC code.

### Claim 13 (depends on 1)

The storage device as set forth in claim 1, wherein the memory controller comprises:
an inverter to invert the plurality of vectors; and
an ECC unit to execute an ECC operation on the plurality of inverted vectors.

### Claim 14 (depends on 13)

The storage device as set forth in claim 13, wherein, during a write operation, the memory controller is configured to encode a write data via the ECC unit, to invert the encoded write data via the inverter, and to write the inverted data into the non-volatile memory device,
wherein, during a read operation, the memory controller is configured to invert read data from the non-volatile memory device via the inverter, and to decode the inverted read data via the ECC unit.

### Claim 15 (depends on 1)

The storage device as set forth in claim 1, wherein the memory controller comprises:
an ECC unit to perform an ECC operation on the plurality of vectors; and
an “all ones” vector detector to detect an “all ones” vector among the plurality of vectors and to inactivate the ECC operation of the ECC unit when an “all ones” vector is detected.

### Claim 16 (depends on 1)

The storage device as set forth in claim 1, wherein the ECC operation is performed during a copy-back operation of the non-volatile memory device.

### Claim 17

A copy-back method of a storage device that includes a non-volatile memory device, the method comprising:
reading data from a source page of the non-volatile memory device;
performing an error correction code (ECC) decoding operation on each of a plurality of vectors in the read data, wherein among the plurality of vectors, a vector corresponding to a clean sector is determined as decoding pass without referring to any flag bit indicating a vector programming state among the plurality of vectors during the ECC decoding operation; and
writing the decoded data via the ECC decoding operation into a target page of the non-volatile memory device.

### Claim 18 (depends on 17)

The method of claim 17, wherein a parity check matrix which generates a zero vector syndrome in a parity check operation in response to an “all ones” vector is supplied for the ECC decoding operation.

### Claim 19 (depends on 17)

The method of claim 17, where the method further comprises:
inverting each of the plurality of vectors in the read data.

### Claim 20 (depends on 17)

The method of claim 17, wherein the method further comprises:
inactivating the ECC decoding operation when a vector among the plurality of vectors corresponds to an “all ones” vector.