# US 8,751,896 B2 · Semiconductor storage device, method of controlling the same, and error correction system

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- Number: US 8,751,896 B2
- Document ID: US8751896B2
- Status: Granted
- Kind: B2
- Application number: 13/939,335
- Filed: 2013-07-11
- Published: 2013-11-07
- Granted: 2014-06-10
- Earliest claimed: 2008-02-29
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Kabushiki Kaisha Toshiba
- Inventors: Akira Yamaga
- Web page: https://patentgrep.com/patent/US8751896B2

## CPC

- G06F 11/1072: {in multilevel memories}
- G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)}
- H03M 13/29: combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M 13/2906: {using block codes (H03M13/2957 takes precedence)}
- G06F 11/1044: {with specific ECC/EDC distribution}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 2029/0411: {Online error correction}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor storage device, a method of controlling the same, and an error correction system allow reduction in power consumption and circuit scale without detriment to error correction capability. An error correction code (ECC) circuit of a solid state drive (SSD) performs first error correction on read data using a first error correction code (Hamming code), and further performs second error correction on the result of the first error correction using a second error correction code (BHC code). Furthermore, the ECC circuit performs third error correction on the result of the second error correction using a third error correction code (RS code).

## Claims

### Claim 1

A apparatus comprising:
a storage device comprising:
a memory module which stores an encoded code word,
a controller which includes a hardwired ECC module which is configured to decode the code word read from the memory module to correct an error included in the code word,
a host device comprising a processor which is configured to receive the code word, and to decode the code word, by executing ECC software, when the error included in the code word is not correctable by the ECC module, wherein an error correcting capability of decoding is stronger with decoding by the processor than decoding by the ECC module.

### Claim 2 (depends on 1)

The apparatus according to claim 1, wherein the memory module comprises NAND Flash memory and a bit length of the code word is an integral multiple of a bit length of the page size of the NAND Flash memory.

### Claim 3 (depends on 1)

The apparatus according to claim 1, wherein the code word comprises a first portion and a second portion, and the ECC module uses the first portion for decoding and the processor uses the second portion for decoding.

### Claim 4

A storage device connectable to a host device, comprising:
a memory module which stores an encoded code word,
a controller which includes a hardwired ECC module which is configured to decode the code word read from the memory module to correct an error included in the code word, and to output the code word to the host device when the error included in the code word is not correctable, so that a processor in the host device is capable of decoding the code word, by executing ECC software.

### Claim 5 (depends on 4)

The device according to claim 4, wherein the memory module comprises NAND Flash memory and a bit length of the code word is an integral multiple of a bit length of a page size of the NAND Flash memory.

### Claim 6 (depends on 5)

The device according to claim 5, wherein the code word comprises a first portion and a second portion, and the ECC module uses the first portion for decoding and the processor uses the second portion for decoding.