# US 8,751,886 B2 · Enable gating select signal to P1500 IR and DR gating

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- Number: US 8,751,886 B2
- Document ID: US8751886B2
- Status: Granted
- Kind: B2
- Application number: 13/909,399
- Filed: 2013-06-04
- Published: 2013-10-17
- Granted: 2014-06-10
- Earliest claimed: 2000-12-22
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Lee D. Whetsel
- Web page: https://patentgrep.com/patent/US8751886B2

## CPC

- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/31713: {Input or output interfaces for test, e.g. test pins, buffers (for scan test G01R31/318572)}
- G01R 31/31723: {Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926)}
- G01R 31/31727: {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922)}
- G01R 31/318508: {Board Level Test, e.g. P1500 Standard (features related to boundary scan G01R31/318533)}
- G01R 31/318555: {Control logic}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.

## Claims

### Claim 1

An integrated circuit comprising:
A. a clock lead, a shift lead, a capture lead, an update lead, a select lead, a serial data in lead, and a serial data out lead;
B. an instruction register coupled to the clock lead, the shift lead, the capture lead, the update lead, the serial data in lead, and the serial data out lead, and having control outputs;
C. an internal scan register coupled to the clock lead, the shift lead, the capture lead, the update lead, the serial data in lead, and the serial data out lead, and having a control input coupled to a control output of the instruction register;
D. a boundary scan register coupled to the clock lead, the shift lead, the capture lead, the update lead, the serial data in lead, and the serial data out lead, and having a control input coupled to a control output of the instruction register;
E. a bypass register coupled to the clock lead, the shift lead, the capture lead, the update lead, the serial data in lead, and the serial data out lead, and having a control input coupled to a control output of the instruction register;
F. first multiplexer circuitry coupled between the internal scan register, the boundary scan register, and the bypass register and the serial data out lead;
G. second multiplexer circuitry connected between the first multiplexer circuitry and the serial data out lead;
H. first gating coupled to the select lead and coupling the clock lead, the shift lead, the capture lead, and the update lead, to the instruction register, the internal scan register, the boundary scan register, and the bypass register;
I. an enable lead; and
J. second gating connected to the enable lead and the select lead and coupling the select lead to the first gating.