# US 8,751,885 B2 · Repair control circuit and semiconductor integrated circuit using the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,751,885 B2 - Document ID: US8751885B2 - Status: Granted - Kind: B2 - Application number: 13/602,244 - Filed: 2012-09-03 - Published: 2013-12-05 - Granted: 2014-06-10 - Earliest claimed: 2012-05-30 - Assignees: SK hynix Inc. - Applicants: Jung Taek You - Inventors: Jung Taek You - Web page: https://patentgrep.com/patent/US8751885B2 ## CPC - G11C 29/4401: {for self repair} - G11C 29/785: {with redundancy programming schemes} - G11C 29/84: {with improved access time or stability} - G11C 2029/1202: {Word line control} - G11C 2029/2602: {Concurrent test} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A repair control circuit and a semiconductor integrated circuit using the same, which can reduce test time, are provided. The semiconductor integrated circuit includes a plurality of memory blocks in which a plurality of word lines are arranged, a plurality of word line drivers driving one or more of the plurality of word lines in response to a plurality of memory block selection signals, and a repair control circuit determining whether to perform a repair through comparison of repair addresses generated in response to surplus addresses and the plurality of memory block selection signals with external addresses. ## Claims ### Claim 1 A repair control circuit comprising: a selection signal generation unit configured to generate selection signals in response to surplus addresses; a selection unit configured to selectively output a plurality of memory block selection signals for selecting one or more of a plurality of memory blocks connected to word lines in response to the selection signals; and a repair address generation unit configured to generate repair addresses in response to the selection signals and outputs of the selection unit. ### Claim 2 (depends on 1) The repair control circuit of claim 1, wherein the selection signal generation unit is configured to generate the selection signals with different levels depending on levels of the surplus addresses. ### Claim 3 (depends on 1) The repair control circuit of claim 1, wherein the selection signal generation unit is configured to generate the selection signals in response to an active signal and the surplus addresses. ### Claim 4 (depends on 1) The repair control circuit of claim 1, wherein the selection signal generation unit is configured to vary values of the selection signals in response to the surplus addresses for an active period of an active signal. ### Claim 5 (depends on 1) The repair control circuit of claim 1, further comprising a comparison unit configured to compare the repair addresses with external addresses and to generate a repair signal. ### Claim 6 (depends on 1) The repair control circuit of claim 1, wherein column addresses are used as the surplus addresses. ### Claim 7 (depends on 1) The repair control circuit of claim 1, further comprising a repair unit configured to activate a repair column selection signal if a repair signal is activated. ### Claim 8 A semiconductor integrated circuit comprising: a plurality of memory blocks in which a plurality of word lines are arranged; a plurality of word line drivers driving one or more of the plurality of word lines in response to a plurality of memory block selection signals; and a repair control circuit determining whether to perform a repair via comparison of repair addresses generated in response to surplus addresses and the plurality of memory block selection signals with external addresses. ### Claim 9 (depends on 8) The semiconductor integrated circuit of claim 8, wherein the surplus addresses have different logic levels for different periods in an active period of a bank active signal. ### Claim 10 (depends on 8) The semiconductor integrated circuit of claim 8, wherein the plurality of memory blocks are divided into a first group and a second group, and the plurality of memory block selection signals are independently allocated to the first group and the second group. ### Claim 11 (depends on 8) The semiconductor integrated circuit of claim 8, wherein the repair control circuit is configured to determine whether to perform the repair with respect to a part of the plurality of memory blocks for a time when the surplus addresses have a first logic level, and to determine whether to perform the repair with respect to the remainder of the part of the plurality of memory blocks for a time when the surplus addresses have a second logic level. ### Claim 12 (depends on 8) The semiconductor integrated circuit of claim 8, wherein the repair control circuit comprises: a selection signal generation unit configured to generate selection signals in response to the surplus addresses; a selection unit configured to selectively output the plurality of memory block selection signals in response to the selection signals; and a repair address generation unit configured to generate the repair addresses in response to the selection signals and outputs of the selection unit. ### Claim 13 (depends on 12) The semiconductor integrated circuit of claim 12, wherein the selection signal generation unit is configured to generate the selection signals with different levels depending on logic levels of the surplus addresses. ### Claim 14 (depends on 12) The semiconductor integrated circuit of claim 12, wherein the selection signal generation unit is configured to generate the selection signals in response to a bank active signal and the surplus addresses. ### Claim 15 (depends on 12) The semiconductor integrated circuit of claim 12, wherein the selection signal generation unit is configured to vary values of the selection signals in response to the surplus addresses for an active period of a bank active signal. ### Claim 16 (depends on 12) The semiconductor integrated circuit of claim 12, wherein specified bits of column addresses are used as the surplus addresses. ### Claim 17 (depends on 12) The semiconductor integrated circuit of claim 12, further comprising a comparison unit configured to compare the repair addresses with external addresses and to generate a repair signal. ### Claim 18 (depends on 12) The semiconductor integrated circuit of claim 12, wherein column addresses are used as the surplus addresses. ### Claim 19 (depends on 12) The semiconductor integrated circuit of claim 12, further comprising a repair unit configured to activate a repair column selection signal if a repair signal is activated.