# US 8,751,883 B2 · Selecting an IC core tap linking module for scanning data

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- Number: US 8,751,883 B2
- Document ID: US8751883B2
- Status: Granted
- Kind: B2
- Application number: 13/941,717
- Filed: 2013-07-15
- Published: 2013-11-14
- Granted: 2014-06-10
- Earliest claimed: 1998-02-18
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Lee D. Whetsel
- Web page: https://patentgrep.com/patent/US8751883B2

## CPC

- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318555: {Control logic}
- G01R 31/318558: {Addressing or selecting of subparts of the device under test}
- G01R 31/318561: {Identification of the subpart}
- G01R 31/318563: {Multiple simultaneous testing of subparts}
- G01R 31/318572: {Input/Output interfaces}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.

## Claims

### Claim 1

A process of accessing an integrated circuit core test access port comprising:
A. powering up an integrated circuit to enable a test access port of the integrated circuit to scan data;
B. scanning instruction data from a test data in lead to an instruction register of the integrated circuit test access port;
C. selecting a hierarchical tap linking module of the integrated circuit for scanning data in response to the instruction data scanned into the instruction register of the integrated circuit test access port;
D. scanning instruction data from the test data in lead to an instruction register of the hierarchical tap linking module of the integrated circuit;
E. enabling the core test access port for scanning data in response to the instruction data scanned into the instruction register of the hierarchical tap linking module of the integrated circuit; and
F. scanning instruction data from the test data in lead to an instruction register of the core test access port.

### Claim 2 (depends on 1)

The process of claim 1 in which the scanning includes scanning in response to a test clock signal and in response to a test mode select signal.

### Claim 3 (depends on 1)

The process of claim 1 in which the enabling includes enabling the core test access port for scanning data partially in response to the instruction data scanned into the instruction register of the hierarchical tap linking module of the integrated circuit and partially in response to powering up the integrated circuit.