# US 8,751,882 B2 · TAP/WRAPPER circuit blocks having two data register control gating circuits

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- Number: US 8,751,882 B2
- Document ID: US8751882B2
- Status: Granted
- Kind: B2
- Application number: 13/894,157
- Filed: 2013-05-14
- Published: 2013-09-26
- Granted: 2014-06-10
- Earliest claimed: 2004-08-20
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Lee D. Whetsel
- Web page: https://patentgrep.com/patent/US8751882B2

## CPC

- G01R 31/31713: {Input or output interfaces for test, e.g. test pins, buffers (for scan test G01R31/318572)}
- G01R 31/28: Testing of electronic circuits, e.g. by signal tracer ({EMC, EMP or similar testing of electronic circuits G01R31/002;} testing for short-circuits, discontinuities, leakage or incorrect line connection G01R31/50; checking computers {or computer components} G06F11/00; checking static stores for correct operation G11C29/00 {; testing receivers or transmitters of transmission systems H04B17/00})
- G01R 31/31724: {Test controller, e.g. BIST state machine (for scan test G01R31/318555)}
- G01R 31/31727: {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922)}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318536: {Scan chain arrangements, e.g. connections, test bus, analog signals}
- G01R 31/318594: {Timing aspects (clock circuits G01R31/318552)}
- G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators}
- G06F 13/287: {Multiplexed DMA (G06F13/30 takes precedence)}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- H03K 19/017509: {Interface arrangements}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

In a first embodiment a Test Access Port (TAP) of IEEE standard 1149.1 is allowed to commandeer control from a Wrapper Serial Port (WSP) of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC (Auxiliary Test Control bus) or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.

## Claims

### Claim 1

An integrated circuit comprising:
A. a test data input lead and a test data output lead;
B. a first bus that includes a test clock lead and a test mode select lead;
C. a second bus that includes a capture lead and a shift lead;
D. plural circuit blocks, each circuit block being a separate test domain, the circuit blocks being serially coupled together between the test data input lead and the test data output lead, each circuit block including:
i. a controller that has inputs coupled to the first bus and that has an instruction register control bus output and a data register control bus output;
ii. instruction register circuitry having a test data input coupled to the test data input lead, control inputs connected to the instruction register control bus, and control outputs;
iii. first gating circuitry having a first input coupled to the data register control bus output, a second input connected to a control output of the instruction register circuitry, third inputs connected to the second bus, and having a first gated data register control output bus;
iv. second gating circuitry having a first inputs coupled to the data register control bus output, second inputs coupled to the first gated data register control output bus, a control input connected to a control output of the instruction register, and second gated data register control bus outputs; and
v. data register circuitry having first inputs coupled to the second gated data register control bus outputs, a test data input coupled to the test data input lead, and a test data output coupled to the test data output lead.

### Claim 2 (depends on 1)

The integrated circuit of claim 1 including a wrapper serial input lead coupled with the test data input lead and a wrapper serial output lead coupled with the test data output lead.

### Claim 3 (depends on 1)

The integrated circuit of claim 1 in which the second bus includes an update lead and a transfer lead.