# US 8,751,773 B2 · Scheduling in a multicore architecture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,751,773 B2 - Document ID: US8751773B2 - Status: Granted - Kind: B2 - Application number: 13/965,124 - Filed: 2013-08-12 - Published: 2014-03-06 - Granted: 2014-06-10 - Earliest claimed: 2005-09-30 - Assignees: Synopsys, Inc.; Fujitsu Semiconductor Limited - Applicants: Synopsys, Inc. - Inventors: Mark David Lippett - Web page: https://patentgrep.com/patent/US8751773B2 ## CPC - G06F 15/80: comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) - G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode - G06F 9/466: {Transaction processing} - G06F 9/4893: {taking into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206)} - G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals} - G06F 9/5038: {considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration (scheduling strategies G06F9/4881 and subgroups)} - G06F 2209/483: Multiproc - G06F 2209/5011: Pool - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract This invention relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue. ## Claims ### Claim 1 A method of scheduling executable transactions in a multicore processor comprising a plurality of processor elements, wherein at least one processor element comprises reconfigurable logic, the method comprising: providing a plurality of executable transaction schedulers, each executable transaction scheduler comprising a scheduling algorithm for determining a most eligible executable transaction for execution from a number of candidate executable transactions; linking the executable transaction schedulers together to form a multilevel scheduler; providing a configuration queue of executable transactions for a first configuration of the reconfigurable logic, the executable transactions allocated to and ready for execution by the reconfigurable logic; outputting a most eligible executable transaction from the multilevel scheduler to the configuration queue; outputting the most eligible executable transaction from the configuration queue to the reconfigurable processor element for execution when the reconfigurable logic is configured according to the first configuration; and reconfiguring the reconfigurable logic according to a second configuration when a pre-determined threshold is reached. ### Claim 2 (depends on 1) The method of claim 1, wherein reconfiguring the reconfigurable logic comprises: stopping the output of executable transactions from the configuration queue associated with the first configuration; reconfiguring the reconfigurable logic according to the second configuration; providing a second configuration queue of executable transactions for the second configuration, the executable transactions of the second configuration queue allocated to and ready for execution by the reconfigurable logic; and outputting the executable transactions of the second configuration queue to the reconfigurable processor element for execution. ### Claim 3 (depends on 1) The method of claim 1, wherein the reconfigurable logic is a memory. ### Claim 4 (depends on 1) The method of claim 1, wherein the pre-determined threshold is a maximum time allowed before a particular executable transaction must be executed. ### Claim 5 (depends on 1) The method of claim 1, wherein the second configuration is selected based on a length of a configuration queue associated with the second configuration. ### Claim 6 (depends on 5) The method of claim 5, wherein the second configuration is selected in response to being associated with the longest configuration queue. ### Claim 7 A non-transitory computer-readable storage medium comprising computer-executable instructions for scheduling executable transactions in a multicore processor comprising a plurality of processor elements, wherein at least one processor element comprises reconfigurable logic, the instructions, when executed, configured to: provide a plurality of executable transaction schedulers, each executable transaction scheduler comprising a scheduling algorithm for determining a most eligible executable transaction for execution from a number of candidate executable transactions; link the executable transaction schedulers together to form a multilevel scheduler; provide a configuration queue of executable transactions for a first configuration of the reconfigurable logic, the executable transactions allocated to and ready for execution by the reconfigurable logic; output a most eligible executable transaction from the multilevel scheduler to the configuration queue; output the most eligible executable transaction from the configuration queue to the reconfigurable processor element for execution when the reconfigurable logic is configured according to the first configuration; and reconfigure the reconfigurable logic according to a second configuration when a pre-determined threshold is reached. ### Claim 8 (depends on 7) The non-transitory computer-readable storage medium of claim 7, wherein reconfiguring the reconfigurable logic comprises: stopping the output of executable transactions from the configuration queue associated with the first configuration; reconfiguring the reconfigurable logic according to the second configuration; providing a second configuration queue of executable transactions for the second configuration, the executable transactions of the second configuration queue allocated to and ready for execution by the reconfigurable logic; and outputting the executable transactions of the second configuration queue to the reconfigurable processor element for execution. ### Claim 9 (depends on 7) The non-transitory computer-readable storage medium of claim 7, wherein the reconfigurable logic is a memory. ### Claim 10 (depends on 7) The non-transitory computer-readable storage medium of claim 7, wherein the pre-determined threshold is a maximum time allowed before a particular executable transaction must be executed. ### Claim 11 (depends on 7) The non-transitory computer-readable storage medium of claim 7, wherein the second configuration is selected based on a length of a configuration queue associated with the second configuration. ### Claim 12 (depends on 11) The non-transitory computer-readable storage medium of claim 11, wherein the second configuration is selected in response to being associated with the longest configuration queue. ### Claim 13 A multicore processor system comprising: a multicore processor comprising a plurality of processor elements, where at least one processor element comprises reconfigurable logic; a plurality of executable transaction schedulers, each executable transaction scheduler comprising a scheduling algorithm for determining a most eligible executable transaction for execution from a number of candidate executable transactions, the plurality of executable transaction schedulers linked together to form a multilevel scheduler, the multilevel scheduler configured to output a most eligible executable transaction; a configuration queue of executable transactions for a first configuration of the reconfigurable logic, the executable transactions allocated to and ready for execution by the reconfigurable logic, the configuration queue configured to receive the most eligible executable transaction and to output the most eligible executable transaction to the reconfigurable processor element for execution when the reconfigurable logic is configured according to the first configuration; and a controller configured to reconfigure the reconfigurable logic according to a second configuration when a pre-determined threshold is reached. ### Claim 14 (depends on 13) The multicore processor system of claim 13, wherein the controller is configured to: stop the output of executable transactions from the configuration queue associated with the first configuration; reconfigure the reconfigurable logic according to the second configuration; provide a second configuration queue of executable transactions for the second configuration, the executable transactions of the second configuration queue allocated to and ready for execution by the reconfigurable logic; and output the executable transactions of the second configuration queue to the reconfigurable processor element for execution. ### Claim 15 (depends on 14) The multicore processor system of claim 14, wherein the reconfigurable logic is a memory. ### Claim 16 (depends on 14) The multicore processor system of claim 14, wherein the pre-determined threshold is a maximum time allowed before a particular executable transaction must be executed. ### Claim 17 (depends on 14) The multicore processor system of claim 14, wherein the second configuration is selected based on a length of a configuration queue associated with the second configuration.