Efficient address generation for pruned interleavers and de-interleavers

An apparatus for processing data, comprising:

• means for receiving a first address for a pruned interleaver;
• one or more circuit means for determining a total number of invalid mappings corresponding to the first address, the one or more circuit means including:
• means for determining a temporary address based on a sum of the first address and an initial value;
• and
• means for determining a first number of invalid mappings in a range of zero to the temporary address,
• wherein the total number of invalid mappings is determined further based on a combination of Dedekind sums;
• means for determining a second address for the pruned interleaver based on the first address and the total number of invalid mappings;
• and
• means for re-ordering data based on the first and second addresses.

A computer program product, comprising:

• a non-transitory computer-readable medium comprising:
• instructions executable by at least one computer to receive a first address for a pruned interleaver,
• instructions executable by the at least one computer to determine a total number of invalid mappings corresponding to the first address at least in part by determining a temporary address based on a sum of the first address and an initial value and by determining a first number of invalid mappings in a range of zero to the temporary address, wherein the total number of invalid mappings is determined further based on a combination of Dedekind sums,
• instructions executable by the at least one computer to determine a second address for the pruned interleaver based on the first address and the total number of invalid mappings, and code for causing the at least one computer to re-order data based on the first and second addresses.