# US 8,751,752 B2 · Invalidating translation lookaside buffer entries in a virtual machine system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,751,752 B2 - Document ID: US8751752B2 - Status: Granted - Kind: B2 - Application number: 13/837,648 - Filed: 2013-03-15 - Published: 2013-08-15 - Granted: 2014-06-10 - Earliest claimed: 2003-09-30 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Eric C. Cota-Robles; Stalinselvaraj Jeyasingh; Alain Kagi; Michael A. Kozuch; Gilbert Neiger; Richard Uhlig - Web page: https://patentgrep.com/patent/US8751752B2 ## CPC - G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] - G06F 9/30076: {to perform miscellaneous control operations, e.g. NOP} - G06F 12/1036: for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) - G06F 2212/151: Emulated environment, e.g. virtual machine - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries. ## Claims ### Claim 1 An apparatus comprising: a translation lookaside buffer (TLB) in a processor having a plurality of TLB entries, each TLB entry being associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to the processor mode when an invalidation operation is performed, the processor mode being one of execution in a virtual machine (VM) and execution not in a virtual machine, the invalidation operation belonging to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries; wherein the invalidation operations include operations (a) task switches involving changes of virtual memory related control registers, or (b) loading of control registers that modify page size extension (PSE) and physical address extension (PAE). ### Claim 2 (depends on 1) The apparatus of claim 1 wherein the invalidation operation is one of (1) a loading of a first control register conditioned on a global bit, (2) an execution of a page invalidate instruction, (3) a task switch involving change of at least one virtual memory related control register (4) a loading of a second control register that modifies one of a protected mode indicator and a page mode indicator, and (5) a loading of a third control register that modifies one of a page size extension (PSE), a page global enable (PGE), and a physical address extension (PAE). ### Claim 3 (depends on 2) The apparatus of claim 2 wherein the processor is in or not in VMX mode and the TLB entry is not invalidated at loading of the first control register when one of a transition into VMX mode (a VM entrance) and a transition out of VMX mode (a VM exit) occurs. ### Claim 4 (depends on 3) The apparatus of claim 3 wherein the VMX tag word is a single hit and the VMX tag word is negated for a new TLB entry when the processor is not in VMX mode and the VMX tag word is asserted for a new TLB entry when the processor is in VMX mode; and the TLB entry is invalidated when an invalidation operation is performed and the VMX tag word is asserted and the processor is in VMX mode. ### Claim 5 (depends on 4) The apparatus of claim 4 wherein the TLB entry is invalidated irrespective of value of the VMX tag word when an invalidation operation is performed and the processor is not in VMX mode. ### Claim 6 (depends on 4) The apparatus of claim 4 wherein a field in a control register is designated the translation lookaside buffer virtual machine extension (TLBVMX) word and the TLB entry is invalidated when an invalidation operation is performed and the VMX tag word matches the TLBVMX word and the processor is not in VMX mode. ### Claim 7 (depends on 3) The apparatus of claim 3 wherein the VMX tag word is a single bit and the VMX tag word is asserted for a new TLB entry When the processor is not in VMX mode and the VMX tag word is negated for a new TLB entry when the processor is in VMX mode; and the TLB entry is invalidated when an invalidation operation is performed and the VMX tag word is negated and the processor is in VMX mode. ### Claim 8 (depends on 7) The apparatus of claim 7 wherein the TLB entry is invalidated irrespective of the value of the VMX tag word when an invalidation operation is performed and the processor is not in VMX mode. ### Claim 9 (depends on 7) The apparatus of claim 7 wherein a field in a control register is designated the TLBVMX word and the TLB entry is invalidated when an invalidation operation is performed and the VMX tag word matches the TLBVMX word and the processor is not in VMX mode. ### Claim 10 (depends on 1) The apparatus of claim 1 wherein invalidation of a TLB entry by an invalidation operation is further conditioned upon value of one or more control words associated with the TLB. ### Claim 11 (depends on 10) The apparatus of claim 10 wherein the control word or words associated with the TLB are located in one or more of the control registers of the processor or in a Virtual Machine Control Structure (VMCS) in memory. ### Claim 12 (depends on 11) The apparatus of claim 11 wherein one of the control words associated with the TLB is distinguished such that the VMX tag word is set to match a distinguished control word for a new TLB entry, the distinguished control word associated with the TLB being designated the TLBVMX word. ### Claim 13 (depends on 12) The apparatus of claim 12 wherein the TLBVMX word is set to one of a plurality of values that constitute a proper subset of a set of all possible values for a VMX tag word when the processor mode corresponds to execution in a virtual machine (VM). ### Claim 14 (depends on 13) The apparatus of claim 13 wherein the TLB entry is invalidated when an invalidation operation is performed and the value of the associated VMX tag word matches the value of the TLBVMX word and the processor mode corresponds to execution in a virtual machine (VM). ### Claim 15 (depends on 14) The apparatus of claim 14 wherein the one or more control words associated with the TLB, including the TLBVMX word, are configurable when the processor mode corresponds to execution not in a virtual machine. ### Claim 16 (depends on 13) The apparatus of claim 13 wherein the TLBVMX word is set to one of a plurality of values that constitute a proper subset of a set of all possible values for a VMX tag word when the processor mode corresponds to execution not in a virtual machine. ### Claim 17 (depends on 16) The apparatus of claim 16 wherein a set theoretic intersection of the plurality of values allowable for the TLBVMX word when the processor mode corresponds to execution not in a virtual machine and the plurality of values allowable for the TLBVMX word when the processor mode corresponds to execution in a virtual machine (VM) is an empty set. ### Claim 18 (depends on 16) The apparatus of claim 16 wherein invalidation of a TLB entry by an invalidation operation is further conditioned upon value of a second control word associated with the TLB when the processor mode corresponds to execution not in a virtual machine. ### Claim 19 (depends on 18) The apparatus of claim 18 wherein the TLB entry is invalidated when an invalidation operation is performed and the associated VMX tag word matches the second control word associated with the TLB and the processor mode corresponds to execution not in a virtual machine. ### Claim 20 (depends on 18) The apparatus of claim 18 wherein the TLB entry is invalidated when an invalidation operation is performed and the logical AND of the associated VMX tag word and the second control word associated with the TLB matches the TLBVMX word and the processor mode corresponds to execution in a virtual machine, the second control word associated with the TLB being designated the TLBVMX mask word.