# US 8,751,749 B2 · Data caching method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,751,749 B2 - Document ID: US8751749B2 - Status: Granted - Kind: B2 - Application number: 13/159,590 - Filed: 2011-06-14 - Published: 2011-12-15 - Granted: 2014-06-10 - Earliest claimed: 2010-06-15 - Assignees: International Business Machines Corporation - Applicants: Christian Habermann; Martin Recktenwald; Hans-Werner Tast; Ralf Winkelmann - Inventors: Christian Habermann; Martin Recktenwald; Hans-Werner Tast; Ralf Winkelmann - Web page: https://patentgrep.com/patent/US8751749B2 ## Abstract Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged. ## Claims ### Claim 1 A computer system comprising: a cache memory hierarchy comprising at least one lower cache memory coupled to a higher cache memory, wherein the computer system is configured to perform a method, said method comprising: receiving by the higher cache memory a fetch request to provide a first line of data; based on receiving the fetch request, determining by the higher cache memory a state of an entry to be replaced next, the entry being for a second line of data different from the requested first line of data; and based on the state of the entry to be replaced next indicating that the entry is exclusively owned or modified, initiating, by the higher cache memory, changing of the state of the entry to be replaced next, wherein based on a subsequent request received by the higher cache memory to provide a third line of data, which is to replace the second line of data in the higher cache memory, an access to replace the second line of data with the third line of data in the higher cache memory will be processed at higher speed compared to an access to replace the second line of data with the third line of data in the higher cache memory responsive to the state of the entry for the second line of data staying unchanged. ### Claim 2 (depends on 1) The computer system of claim 1, wherein the first line of data and the entry to be replaced pertain to a same congruence class. ### Claim 3 (depends on 1) The computer system of claim 1, wherein changing the state of the entry to be replaced next comprises setting to a state indicating that the entry is valid but may be set to invalid at any time. ### Claim 4 (depends on 1) The computer system of claim 1, wherein a lower cache memory of the at least one lower cache memory maintains a copy of the second line of data, and wherein changing the state comprises the higher cache memory sending a cross interrogate command to the lower cache memory to indicate the change to the state. ### Claim 5 (depends on 1) The computer system of claim 1, wherein changing the state comprises demoting the entry to shared. ### Claim 6 A computer program product for caching data in a computer system comprising a buffer memory comprising at least one lower cache memory coupled to a higher cache memory, said computer program product comprising: a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising: receiving by the higher cache memory a fetch request to provide a first line of data; based on receiving the fetch request, determining by the higher cache memory a state of an entry to be replaced next, the entry being for a second line of data different from the requested first line of data; and based on the state of the entry to be replaced next indicating that the entry is exclusively owned or modified, initiating, by the higher cache memory, changing of the state of the entry to be replaced next, wherein based on a subsequent request received by the higher cache memory to provide a third line of data, which is to replace the second line of data in the higher cache memory, an access to replace the second line of data with the third line of data in the higher cache memory will be processed at higher speed compared to an access to replace the second line of data with the third line of data in the higher cache memory responsive to the state of the entry for the second line of data staying unchanged. ### Claim 7 (depends on 6) The computer program product of claim 6, wherein the first line of data and the entry to be replaced pertain to a same congruence class. ### Claim 8 (depends on 6) The computer program product of claim 6, wherein changing the state of the entry to be replaced next comprises setting to a state indicating that the entry is valid but may be set to invalid at any time. ### Claim 9 (depends on 6) The computer program product of claim 6, wherein a lower cache memory of the at least one lower cache memory maintains a copy of the second line of data, and wherein changing the state comprises the higher cache memory sending a cross interrogate command sent to the lower cache memory to indicate the change to the state. ### Claim 10 (depends on 6) The computer program product of claim 6, wherein changing the state comprises demoting the entry to shared. ### Claim 11 (depends on 1) The computer system of claim 1, wherein changing the state of the entry comprises the higher cache memory sending a command to a lower cache memory, and the lower cache memory changing a state of a maintained copy of the second line of data from valid to another state. ### Claim 12 (depends on 6) The computer program product of claim 6, wherein changing the state of the entry comprises the higher cache memory sending a command to a lower cache memory, and the lower cache memory changing a state of a maintained copy of the second line of data from valid to another state.