# US 8,751,744 B2 · Integrated circuit comprising trace logic and method for providing trace information > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,751,744 B2 - Document ID: US8751744B2 - Status: Granted - Kind: B2 - Application number: 13/318,542 - Filed: 2009-05-29 - Published: 2012-03-22 - Granted: 2014-06-10 - Earliest claimed: 2009-05-29 - Assignees: Freescale Semiconductor, Inc. - Applicants: Bertrand Deleris; Rich Collins - Inventors: Bertrand Deleris; Rich Collins - Web page: https://patentgrep.com/patent/US8751744B2 ## CPC - G06F 11/3636: {by tracing the execution of the program} - G06F 11/364: {tracing values on a bus} - G06F 11/3648: {using additional hardware} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An integrated circuit comprises trace logic for operably coupling to at least one memory element and for providing trace information for a signal processing system. The trace logic comprises trigger detection logic for detecting at least one trace trigger, memory access logic arranged to perform, upon detection of the at least one trace trigger, at least one read operation for at least one memory location of the at least one memory element associated with the at least one detected trigger, memory content message generation logic arranged to generate at least one memory content message comprising information relating to a result of the at least one read operation performed by the memory access logic, and output logic for outputting the at least one memory content message. ## Claims ### Claim 1 An integrated circuit (IC) comprising: trace logic for operably coupling to a system memory element and for providing trace information for a signal processing system, the trace logic comprising: trigger detection logic for detecting a trace trigger in response to a first address being transmitted on a virtual bus between a system core element and a cache memory element; memory access logic arranged to provide a read request to memory access arbitration hardware, in response to the trace trigger, for data information stored at the system memory element; in response to receiving the data information, message generation logic arranged to generate a first trace message comprising the data information; and output logic for outputting the first trace message. ### Claim 2 (depends on 1) The integrated circuit of claim 1 wherein the trigger detection logic is arranged, in response to the trigger detection logic detecting the trace trigger, to generate a second trace message for outputting by the output logic indicating the trace trigger was detected. ### Claim 3 (depends on 2) The integrated circuit of claim 2 wherein the trace logic further comprises message queuing logic for queuing the first and second trace messages for output by the output logic. ### Claim 4 (depends on 3) The integrated circuit of claim 3 wherein the trigger detection logic is operably coupled to the virtual bus of the signal processing system, and is arranged to detect the first address being transmitted on the virtual bus between the system core element and the cache memory element. ### Claim 5 (depends on 2) The integrated circuit of claim 2 wherein the trigger detection logic is operably coupled to the virtual bus of the signal processing system, and is arranged to detect the first address being transmitted on the virtual bus between the system core element and the cache memory element. ### Claim 6 (depends on 1) The integrated circuit of claim 1 wherein the trigger detection logic is operably coupled to the virtual bus of the signal processing system, and is arranged to detect the first address being transmitted on the virtual bus between the system core element and the cache memory element. ### Claim 7 (depends on 1) The integrated circuit of claim 1 wherein an address accessed by the read request, in response to the trace trigger, is configurable. ### Claim 8 (depends on 1) The integrated circuit of claim 1 wherein the memory access logic comprises direct memory access (DMA) logic operably coupled to the system memory element of the signal processing system. ### Claim 9 (depends on 1) The integrated circuit of claim 1 wherein the output logic is arranged to output the first trace message to at least one from a group of: a trace port; a virtual trace buffer within the system memory element; and a dedicated trace buffer. ### Claim 10 (depends on 1) The Integrated circuit of claim 1 wherein the first address comprises at least one from a group of: an indication of a change of program flow; an indication of a specific data access; a process address; a data address. ### Claim 11 (depends on 1) The Integrated circuit of claim 1 wherein the trace logic is a hardware trace module. ### Claim 12 (depends on 1) The Integrated circuit of claim 1 wherein the trace logic is operably coupled to a trace port and at least one from the following group is arranged to be configurable via the trace port: the trace trigger to be detected by the trigger detection logic; an address accessed by the read request; a memory size associated with the read request. ### Claim 13 A method for providing trace information for a signal processing system, the method comprising: generating a trace trigger in response to a first address being transmitted on a virtual bus between a system core element and a cache memory element; in response to the trace trigger, providing a read request to arbitration hardware from a trace module for data information of a system memory; receiving the data information at the trace module as a result of the read request; generating, by the trace module, a first trace message comprising the data information; and outputting the first trace message. ### Claim 14 (depends on 13) The method of claim 13, wherein generating the trace trigger is further in response to the first address matching a stored address. ### Claim 15 (depends on 13) The method of claim 13, wherein the first address being transmitted comprises an indication of a change of program flow. ### Claim 16 (depends on 13) The method of claim 13, wherein the first address being transmitted comprises a process address. ### Claim 17 (depends on 13) The method of claim 13, wherein the first address being transmitted comprises an indication of a specific data access. ### Claim 18 (depends on 13) The method of claim 13, wherein the first address being transmitted comprises a data address. ### Claim 19 A method for providing trace information for a signal processing system, the method comprising: generating a trace trigger in response to an address corresponding to first data information being transmitted; in response to the trace trigger, performing a read operation at a memory location that includes the address; generating a memory content trace message comprising the first data information read from the memory location; and outputting the memory content trace message. ### Claim 20 (depends on 19) The method of claim 19, wherein the read operation is between a trace logic and a system memory via an arbitration hardware; and wherein the first data information read from the memory location is received by the trace logic from the system memory via the arbitration hardware.