# US 8,751,736 B2 · Instructions to set and read memory version information > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,751,736 B2 - Document ID: US8751736B2 - Status: Granted - Kind: B2 - Application number: 13/196,514 - Filed: 2011-08-02 - Published: 2013-02-07 - Granted: 2014-06-10 - Earliest claimed: 2011-08-02 - Assignees: Oracle International Corporation - Applicants: Zoran Radovic; Darryl J. Gove; Graham Ricketson Murphy - Inventors: Zoran Radovic; Darryl J. Gove; Graham Ricketson Murphy - Web page: https://patentgrep.com/patent/US8751736B2 ## CPC - G06F 11/0763: {by bit configuration check, e.g. of formats or tags} - G06F 9/3824: {Operand accessing} - G06F 9/3834: {Maintaining memory consistency} - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Systems and methods for providing additional instructions for supporting efficient memory corruption detection in a processor. A physical memory may be a DRAM with a spare bank of memory reserved for a hardware failover mechanism. Version numbers associated with data structures allocated in the memory may be generated so that version numbers of adjacent data structures are different. A processor determines that a fetched instruction is a memory access instruction corresponding to a first data structure within the memory. For instructions that are not a version update instruction, the processor compares the first version number and second version number stored in a location in the memory indicated by the generated address and flags an error if there is a mismatch. For version update instructions, the processor performs a memory access operation on the second version number with no comparison check. ## Claims ### Claim 1 A computing system comprising: a physical memory, wherein the physical memory is configured to store one or more data structures, each with an associated version number; and a processor coupled to the memory, wherein the processor is configured to: receive an instruction; determine the instruction is a memory access instruction corresponding to a first data structure of the one or more data structures; and generate a pointer corresponding to a location within the first data structure, wherein bits used to form the pointer include both an address and a first version number associated with the first data structure; wherein the physical memory comprises a plurality of banks, and wherein the first data structure is stored in a first bank of the plurality of banks, and a second version number associated with the first data structure is stored in a spare bank corresponding to the first bank, wherein in response to said instruction, the processor is further configured to: access the second version number stored in the memory; compare the first version number to the second version number; and detect an error in response to determining the first version number does not match the second version number. ### Claim 2 (depends on 1) The computing system as recited in claim 1, wherein in response to determining the instruction is a store instruction, the processor is further configured to: overwrite the second version number with the first version number; and overwrite data stored in first bank with store data associated with the store instruction. ### Claim 3 (depends on 2) The computing system as recited in claim 2, wherein in response to determining the instruction is a block initialization store instruction, the processor is further configured to utilize initialization data for the store data. ### Claim 4 (depends on 2) The computing system as recited in claim 2, wherein the instruction is used to copy data corresponding to the first version number from a disk to the physical memory. ### Claim 5 (depends on 1) The computing system as recited in claim 1, wherein in response to determining the instruction is a version update load instruction, the processor is further configured to: read the second version number from the location in the physical memory indicated by the pointer; and store the second version number in a destination register indicated by the load instruction, wherein the destination register does not store a copy of the data stored in the location in the physical memory. ### Claim 6 (depends on 5) The computing system as recited in claim 5, wherein contents of the destination register are used for a copy operation for the first array from the physical memory to another level of memory within a memory subsystem. ### Claim 7 A method for a processor, the method comprising: receiving an instruction; determining the instruction is a memory access instruction corresponding to a first data structure of one or more data structures stored in a physical memory, each with an associated version number; and generating a pointer corresponding to a location within the first data structure, wherein bits used to form the pointer include both an address and a first version number associated with the first data structure; wherein the physical memory comprises a plurality of banks, and wherein the first data structure is stored in a first bank of the plurality of banks, and a second version number associated with the first data structure is stored in a spare bank corresponding to the first bank, wherein in response to said instruction, the method further comprises: accessing the second version number stored in the memory; comparing the first version number to the second version number; and detecting an error in response to determining the first version number does not match the second version number. ### Claim 8 (depends on 7) The method as recited in claim 7, wherein in response to determining the instruction is a store instruction, the method further comprises: overwriting the second version number with the first version number; and overwriting data stored in a location in the physical memory indicated by the pointer with store data associated with the store instruction. ### Claim 9 (depends on 8) The method as recited in claim 8, wherein in response to determining the instruction is a block initialization store instruction, the method further comprises utilizing initialization data for the store data. ### Claim 10 (depends on 8) The method as recited in claim 8, wherein the instruction is used to copy data corresponding to the first version number from a disk to the physical memory. ### Claim 11 (depends on 9) The method as recited in claim 9, wherein in response to determining the instruction is a version update load instruction, the method further comprises: reading the second version number from the location in the physical memory indicated by the pointer; and storing the second version number in a destination register indicated by the load instruction, wherein the destination register does not store a copy of the data stored in the location in the physical memory. ### Claim 12 (depends on 11) The method as recited in claim 11, further comprising using contents of the destination register for a copy operation for the first array from the physical memory to another level of memory within a memory subsystem. ### Claim 13 A processor comprising: an instruction fetch unit configured to fetch instructions from a memory subsystem comprising a physical memory, wherein the physical memory is configured to store one or more data structures, each with an associated version number; a decoder coupled to the instruction fetch unit; an execution unit; and wherein the decoder is configured to: receive an instruction; and determine the instruction is a memory access instruction corresponding to a first data structure of the one or more data structures; wherein the execution unit is configure to generate a pointer corresponding to a location within the first data structure, wherein bits used to form the pointer include both an address and a first version number associated with the first data structure; and wherein the physical memory comprises a plurality of banks, and wherein the first data structure is stored in a first bank of the plurality of banks, and a second version number associated with the first data structure is stored in a spare bank corresponding to the first bank, wherein in response to said instruction, the processor is further configured to: access the second version number stored in the memory; compare the first version number to the second version number; and detect an error in response to determining the first version number does not match the second version number. ### Claim 14 (depends on 13) The processor as recited in claim 13, wherein in response to receiving an indication from the decoder that the instruction is a version update load instruction, the processor is further configured to: read the second version number from the location in the physical memory indicated by the pointer; and store the second version number in a destination register indicated by the load instruction, wherein the destination register does not store a copy of the data stored in the location in the physical memory.