# US 8,751,735 B2 · Protection against data corruption for multi-level memory cell (MLC) flash memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,751,735 B2 - Document ID: US8751735B2 - Status: Granted - Kind: B2 - Application number: 14/039,585 - Filed: 2013-09-27 - Published: 2014-01-23 - Granted: 2014-06-10 - Earliest claimed: 2010-02-17 - Assignees: Marvell World Trade Ltd. - Applicants: Marvell World Trade Ltd. - Inventors: Qun Zhao; Xinhai Kang - Web page: https://patentgrep.com/patent/US8751735B2 ## CPC - G11C 16/10: Programming or data input circuits - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles} - G11C 2211/5641: Multilevel memory having cells with different number of storage levels - G11C 2211/5643: Multilevel memory comprising cache storage devices - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A system including a controller in communication with a memory. The memory includes memory cells arranged in memory blocks. Each memory cell is capable of storing a plurality of bits. Each memory block defines a plurality of pages. A page in a memory block includes one of the plurality of bits of a plurality of memory cells in the memory block. The controller is configured to write data to selected pages in one or more memory blocks. The system includes circuitry configured to write data from a predetermined number of pages of the selected pages to a memory block other than the one or more memory blocks in response to the predetermined number of pages being full of data. The predetermined number is based on one or more of a number of pages in each memory block and a number of bits in the plurality of bits. ## Claims ### Claim 1 A system comprising: a controller in communication with a memory, wherein the memory includes memory cells arranged in memory blocks, wherein each memory cell is capable of storing a plurality of bits, wherein each memory block defines a plurality of pages, wherein a page in a memory block includes one of the plurality of bits of a plurality of memory cells in the memory block, and wherein the controller is configured to write data to selected pages in one or more memory blocks; and circuitry configured to write data from a predetermined number of pages of the selected pages to a memory block other than the one or more memory blocks in response to the predetermined number of pages being full of data, wherein the predetermined number is based on one or more of (i) a number of pages in each memory block and (ii) a number of bits in the plurality of bits. ### Claim 2 (depends on 1) The system of claim 1, wherein the circuitry is configured to erase data from the predetermined number of pages subsequent to the data from the predetermined number of pages being written to the memory block other than the one or more memory blocks. ### Claim 3 (depends on 1) The system of claim 1, wherein the one of the plurality of bits includes (i) a least significant bit, (ii) a most significant bit, or (iii) one or more bits other than the least significant bit and the most significant bit. ### Claim 4 (depends on 1) The system of claim 1, wherein the predetermined number is selected based on a ratio of the number of pages in each memory block to the number of bits in the plurality of bits. ### Claim 5 (depends on 1) The system of claim 1, wherein the predetermined number is selected based on the number of bits in the plurality of bits. ### Claim 6 (depends on 1) The system of claim 1, wherein the predetermined number is selected to be greater or less than the number of bits in the plurality of bits. ### Claim 7 (depends on 1) The system of claim 1, wherein the predetermined number is measured over one or more memory blocks. ### Claim 8 (depends on 1) The system of claim 1, wherein the circuitry is configured to write the data from the predetermined number of pages to the memory block other than the one or more memory blocks without using additional memory external to (i) the controller and (ii) the memory. ### Claim 9 (depends on 1) The system of claim 1, wherein the memory includes flash memory. ### Claim 10 (depends on 1) The system of claim 1, further comprising a host processor to provide the data to be written to the memory. ### Claim 11 A method for writing data to a memory, wherein the memory includes memory cells arranged in memory blocks, wherein each memory cell is capable of storing a plurality of bits, wherein each memory block defines a plurality of pages, and wherein a page in a memory block includes one of the plurality of bits of a plurality of memory cells in the memory block, the method comprising: writing data to selected pages in one or more memory blocks; and writing data from a predetermined number of pages of the selected pages to a memory block other than the one or more memory blocks in response to the predetermined number of pages being full of data, wherein the predetermined number is based on one or more of (i) a number of pages in each memory block and (ii) a number of bits in the plurality of bits. ### Claim 12 (depends on 11) The method of claim 11, further comprising erasing data from the predetermined number of pages subsequent to the data from the predetermined number of pages being written to the memory block other than the one or more memory blocks. ### Claim 13 (depends on 11) The method of claim 11, wherein the one of the plurality of bits includes (i) a least significant bit, (ii) a most significant bit, or (iii) one or more bits other than the least significant bit and the most significant bit. ### Claim 14 (depends on 11) The method of claim 11, further comprising selecting the predetermined number based on a ratio of the number of pages in each memory block to the number of bits in the plurality of bits. ### Claim 15 (depends on 11) The method of claim 11, further comprising selecting the predetermined number based on the number of bits in the plurality of bits. ### Claim 16 (depends on 11) The method of claim 11, further comprising selecting the predetermined number to be greater or less than the number of bits in the plurality of bits. ### Claim 17 (depends on 11) The method of claim 11, further comprising measuring the predetermined number over one or more memory blocks. ### Claim 18 (depends on 11) The method of claim 11, further comprising writing the data from the predetermined number of pages to the memory block other than the one or more memory blocks without using additional memory external to the memory. ### Claim 19 (depends on 11) The method of claim 11, wherein the memory includes flash memory. ### Claim 20 (depends on 11) The method of claim 11, further comprising receiving the data to be written to the memory from a host processor.