# US 8,751,709 B2 · Hybrid interface for serial and parallel communication > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,751,709 B2 - Document ID: US8751709B2 - Status: Granted - Kind: B2 - Application number: 13/934,147 - Filed: 2013-07-02 - Published: 2013-10-31 - Granted: 2014-06-10 - Earliest claimed: 2010-02-11 - Assignees: Silicon Image, Inc. - Applicants: Silicon Image, Inc. - Inventors: Alan T. Ruberg; Roger Isaac - Web page: https://patentgrep.com/patent/US8751709B2 ## CPC - G06F 13/4204: {on a parallel bus} - G06F 13/4045: {where the bus bridge performs an extender function} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Embodiments of the invention are generally directed to a hybrid interface for serial and parallel communication. An embodiment of a method includes initializing a first apparatus for transmission of data to or reception of data from a second apparatus, switching an interface for the first apparatus to a first mode for a parallel interface, the parallel interface including a first plurality of pins, and transmitting or receiving parallel data in the first mode via the first plurality of pins. The method further includes switching the interface of the first apparatus to a second mode for a serial interface, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, and transmitting or receiving serial data in the second mode via the second plurality of pins. ## Claims ### Claim 1 A method comprising: selecting a first mode or a second mode of communication between a first apparatus and a second apparatus using a first control, the first control being a mode control, the first apparatus including a reference oscillator circuit, wherein: the first mode is a parallel interface mode for a parallel interface between the first apparatus and the second apparatus, the parallel interface including a first plurality of pins, and the second mode is a serial interface mode for a serial interface between the first apparatus and the second apparatus, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, the reference oscillator circuit being used to provide clocking for data transfer in the second mode; providing the selected mode of communication and communicating data between the first apparatus and the second apparatus using the selected mode of communication; and enabling or disabling the reference oscillator circuit using a second control, the second control being a reference oscillator control independent of the first control. ### Claim 2 (depends on 1) The method of claim 1, wherein the reference oscillator circuit is enabled during the parallel interface mode. ### Claim 3 (depends on 2) The method of claim 2, wherein the reference oscillator circuit is enabled before the serial interface mode is selected. ### Claim 4 (depends on 2) The method of claim 2, wherein the reference oscillator circuit is enabled after the parallel interface mode is selected. ### Claim 5 (depends on 2) The method of claim 2, wherein the reference oscillator remains enabled during a time period from when the parallel interface mode is selected until the serial interface mode is selected. ### Claim 6 (depends on 1) The method of claim 1, wherein the reference oscillator circuit is disabled during the parallel interface mode. ### Claim 7 (depends on 1) The method of claim 1, wherein the reference oscillator circuit is disabled automatically when the parallel interface mode is selected. ### Claim 8 (depends on 1) The method of claim 1, wherein the reference oscillator circuit provides a signal indicating readiness for serial communication. ### Claim 9 (depends on 8) The method of claim 8, wherein the serial interface mode is selected based on reference oscillator readiness. ### Claim 10 A method comprising: communicating data between a first apparatus and a second apparatus, the first apparatus including a reference oscillator circuit and a CDR (clock data recovery) circuit, the first apparatus and the second apparatus communicating in either a first mode or a second mode, wherein: the first mode is a mode providing a parallel interface between the first apparatus and the second apparatus, the parallel interface including a first plurality of pins; the second mode is a mode providing a serial interface between the first apparatus and the second apparatus, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins; enabling or disabling the reference oscillator circuit using a reference oscillator control; and enabling or disabling the CDR circuit using a CDR control that is independent of the reference oscillator control. ### Claim 11 (depends on 10) The method of claim 10, wherein the CDR circuit is enabled while the reference oscillator circuit is functioning. ### Claim 12 (depends on 10) The method of claim 10, wherein the CDR circuit is disabled while the reference oscillator circuit is functioning. ### Claim 13 (depends on 10) The method of claim 10, wherein the CDR circuit is enabled coincident to when the reference oscillator circuit is enabled. ### Claim 14 (depends on 10) The method of claim 10, wherein the CDR circuit is disabled coincident to when the reference oscillator circuit is enabled. ### Claim 15 An apparatus including: an interface with a second apparatus, wherein the interface may be selected to be in a first mode or a second mode of communication, the selection being made using a first control, the first control being a mode control, wherein: the first mode is a parallel interface mode to provide a parallel interface between the apparatus and the second apparatus, the parallel interface including a first plurality of pins, and the second mode is a serial interface mode to provide a serial interface between the apparatus and the second apparatus, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, the reference oscillator circuit used for data transfer; and a reference oscillator circuit, wherein the reference oscillator circuit is enabled or disabled by a second control, the second control being a reference oscillator control independent of the first control. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein the reference oscillator circuit is enabled during the parallel interface mode. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein the reference oscillator circuit is enabled before the serial interface mode is selected. ### Claim 18 (depends on 16) The apparatus of claim 16, wherein the reference oscillator circuit is enabled after the parallel interface mode is selected. ### Claim 19 (depends on 16) The apparatus of claim 16, wherein the reference oscillator remains enabled during a time period from when the parallel interface mode is selected until the serial interface mode is selected. ### Claim 20 (depends on 15) The apparatus of claim 15, wherein the reference oscillator circuit is disabled during the parallel interface mode. ### Claim 21 (depends on 15) The apparatus of claim 15, wherein the reference oscillator circuit is disabled automatically when the parallel interface mode is selected. ### Claim 22 (depends on 15) The apparatus of claim 15, wherein the reference oscillator circuit provides a signal indicating readiness for serial communication. ### Claim 23 (depends on 22) The apparatus of claim 22, wherein the serial interface mode is selected based on reference oscillator readiness. ### Claim 24 An apparatus including: an interface with a second apparatus, wherein the interface may be selected to be in a first mode or a second mode of communication, wherein: the first mode is a parallel interface mode to provide a parallel interface between the apparatus and the second apparatus, the parallel interface including a first plurality of pins, and the second mode is a serial interface mode to provide a serial interface between the apparatus and the second apparatus, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, the reference oscillator circuit used for data transfer; a reference oscillator circuit, wherein the reference oscillator circuit is enabled or disabled by a reference oscillator control; and a CDR (clock data recovery) circuit, wherein the CDR circuit is enabled or disabled by a CDR control that is independent of the reference oscillator control. ### Claim 25 (depends on 24) The apparatus of claim 24, wherein the CDR circuit is enabled while the reference oscillator circuit is functioning. ### Claim 26 (depends on 24) The apparatus of claim 24, wherein the CDR circuit is disabled while the reference oscillator circuit is functioning. ### Claim 27 (depends on 24) The apparatus of claim 24, wherein the CDR circuit is enabled coincident to when the reference oscillator circuit is enabled. ### Claim 28 (depends on 24) The apparatus of claim 24, wherein the CDR circuit is disabled coincident to when the reference oscillator circuit is enabled.