# US 8,751,182 B2 · System and method for testing serial ports > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,751,182 B2 - Document ID: US8751182B2 - Status: Granted - Kind: B2 - Application number: 13/209,449 - Filed: 2011-08-15 - Published: 2012-04-19 - Granted: 2014-06-10 - Earliest claimed: 2010-10-14 - Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.; Hon Hai Precision Industry Co., Ltd. - Applicants: Zhi-Jian Long; Ming-Xiang Hu; Jun-Min Chen; Le Lin; Xiao-Fei Chen - Inventors: Zhi-Jian Long; Ming-Xiang Hu; Jun-Min Chen; Le Lin; Xiao-Fei Chen - Web page: https://patentgrep.com/patent/US8751182B2 ## CPC - G06F 11/221: {to test buses, lines or interfaces, e.g. stuck-at or open line faults} - G06F 11/2221: {to test input/output devices or peripheral units} - G06F 11/2284: {by power-on test, e.g. power-on self test [POST]} - G06F 11/25: Testing of logic operation, e.g. by logic analysers - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In a system and method for testing a serial port of a computing device, the serial port electronically connects to a test fixture. Test data is sent to a receive data (RXD) pin by a transmit data (TXD) pin. A test result is received from the serial port by the RXD pin. The TXD pin and the RXD pin work normally if the test data is identical to the test result. When voltages of a request to send (RTS) pin and a data terminal ready (DTR) pin are set at high level, the RTS pin, a data carrier detect (DCD) pin, the DTR pin, a ring indicator (RI) pin, a data send ready (DSR) pin and a clear to send (CTS) pin work normally, upon the condition that status values of the serial port indicate the voltages of the above six pins are at high level. ## Claims ### Claim 1 A computing device, comprising: a storage system; at least one processor; a motherboard comprising a serial port; and one or more programs stored in the storage system and executed by the at least one processor, the one or more programs comprising: a sending module operable to enable a transmit data (TXD) pin of the serial port to send test data to a receive data (RXD) pin of the serial port; an acquisition module operable to enable the RXD pin to receive a test result from the serial port, and acquire status values of the serial port; a determination module operable to compare the test data with the test result, and determine that the TXD pin and the RXD pin work normally upon the condition that the test data is identical to the test result; a setting module operable to set voltages of a data terminal ready (DTR) pin and a request to send (RTS) pin of the serial port at high level; the determination module further operable to determine that the RTS pin and a data carrier detect (DCD) pin of the serial port work normally, upon the condition that the status values indicate the voltages of the RTS pin and the DCD pin are at high level; the determination module further operable to determine that the DTR pin and a ring indicator (RI) pin of the serial port work normally, upon the condition that the status values indicate the voltages of the DTR pin and the RI pin are at high level; and the determination module further operable to determine that a data send ready (DSR) pin and a clear to send (CTS) pin of the serial port work normally, upon the condition that the status values indicate the voltages of the DSR pin and the CTS pin are at high level. ### Claim 2 (depends on 1) The computing device of claim 1, wherein the serial port electronically connects to a test fixture that comprises four npn transistors, and the four npn transistors connect to the serial port to form five circuit loops that comprise: a first circuit loop that is formed by connecting the TxD pin to the RXD pin; a second circuit loop that is formed by connecting the DTR pin to a base of a first transistor, connecting the RTS pin to a collector of the first transistor, and connecting the CTS pin to an emitter of the first transistor; a third circuit loop that is formed by connecting the TXD pin to a base of a second transistor, connecting the DTR pin to a collector of the second transistor, and connecting the RI pin to an emitter of the second transistor; a fourth circuit loop that is formed by connecting the RTS pin to a base of a third transistor, connecting the DTR pin to a collector of the third transistor, and connecting the DSR pin to an emitter of the third transistor; and a fifth circuit loop that is formed by connecting the TXD pin to a base of a fourth transistor, connecting the RTS pin to a collector of the fourth transistor, and connecting the DCD pin to an emitter of the fourth transistors. ### Claim 3 (depends on 1) The computing device of claim 1, further comprising an initialization module that is operable to initialize the serial port according to predetermined configuration information. ### Claim 4 (depends on 1) The computing device of claim 1, wherein the status values are logic 0 or logic 1. ### Claim 5 (depends on 1) The computing device of claim 1, wherein the determination module is further operable to determine that the RTS pin and the DCD pin do not work normally, upon the condition that the status values indicate the voltages of the RTS pin and the DCD pin are not at high level. ### Claim 6 (depends on 1) The computing device of claim 1, wherein the determination module is further operable to determine that the DTR pin and the RI pin do nor work normally, upon the condition that the status values indicate the voltages of the DTR pin and the RI pin are not at high level. ### Claim 7 (depends on 1) The computing device of claim 1, wherein the determination module is further operable to determine that the DSR pin and the CTS pin do not work normally, upon the condition that the status values indicate the voltages of the DSR pin and the CTS pin are not at high level. ### Claim 8 A method for testing a serial port of a computing device, the method comprising: (a) enabling a transmit data (TXD) pin of the serial port to send test data to a receive data (RXD) pin of the serial port, and enabling the RXD pin to receive a test result from the serial port; (b) comparing the test data with the test result, and determining that the TXD pin and the RXD pin work normally upon the condition that the test data is identical to the test result; (c) acquiring a first status values of the serial port when a voltage of a request to send (RTS) pin of the serial port is set at high level; (d) determining that the RTS pin and a data carrier detect (DCD) pin of the serial port work normally, upon the condition that the first status values indicate the voltages of the RTS pin and the DCD pin are at high level; (e) acquiring a second status values of the serial port when a voltage of a data terminal ready (DTR) pin of the serial port is set at high level; (f) determining that the DTR pin and a ring indicator (RI) pin of the serial port work normally, upon the condition that the second status values indicate the voltages of the DTR pin and the RI pin are at high level; (g) acquiring a third status values of the serial port when the voltages of the RTS pin and DTR pin are set at high level; and (h) determining that a data send ready (DSR) pin and a clear to send (CTS) pin of the serial port work normally, upon the condition that the third status values indicate the voltages of the DSR pin and the CTS pin are at high level. ### Claim 9 (depends on 8) The method of claim 8, wherein the serial port electronically connects to a test fixture that comprises four npn transistors, and the four npn transistors connect to the serial port to form five circuit loops that comprise: a first circuit loop that is formed by connecting the TXD pin to the RXD pin; a second circuit loop that is formed by connecting the DTR pin to a base of a first transistor, connecting the RTS pin to a collector of the first transistor, and connecting the CTS pin to an emitter of the first transistor; a third circuit loop that is formed by connecting the TXD pin to a base of a second transistor, connecting the DTR pin to a collector of the second transistor, and connecting the RI pin to an emitter of the second transistor; a fourth circuit loop that is formed by connecting the RTS pin to a base of a third transistor, connecting the DTR pin to a collector of the third transistor, and connecting the DSR pin to an emitter of the third transistor; and a fifth circuit loop that is formed by connecting the TXD pin to a base of a fourth transistor, connecting the RTS pin to a collector of the fourth transistor, and connecting the DCD pin to an emitter of the fourth transistors. ### Claim 10 (depends on 8) The method of claim 8, further comprising: initializing the serial port according to predetermined configuration information. ### Claim 11 (depends on 8) The method of claim 8, wherein the step (d) comprises: determining that the RTS pin and the DCD pin do not work normally, upon the condition that the first status values indicate the voltages of the RTS pin and the DCD pin are not at high level. ### Claim 12 (depends on 8) The method of claim 8, wherein the step (f) comprises: determining that the DTR pin and the RI pin do not work normally, upon the condition that the second status values indicate the voltages of the DTR pin and the RI pin are not at high level. ### Claim 13 (depends on 8) The method of claim 8, wherein the step (h) comprises: determining that the DSR pin and the CTS pin do not work normally, upon the condition that the third status values indicate the voltages of the DSR pin and the CTS pin are not at high level. ### Claim 14 A non-transitory storage medium storing a set of instructions, the set of instructions capable of being executed by a processor of a computing device, causes the computing device to execute a method for testing a serial port of the computing device, the method comprising: (a) enabling a transmit data (TXD) pin of the serial port to send test data to a receive data (RXD) pin of the serial port, and enabling the RXD pin to receive a test result from the serial port; (b) comparing the test data with the test result, and determining that the TXD pin and the RXD pin work normally upon the condition that the test data is identical to the test result; (c) acquiring a first status values of the serial port when a voltage of a request to send (RTS) pin of the serial port is set at high level; (d) determining that the RTS pin and a data carrier detect (DCD) pin of the serial port work normally, upon the condition that the first status values indicate the voltages of the RTS pin and the DCD pin are at high level; (e) acquiring a second status values of the serial port when a voltage of a data terminal ready (DTR) pin of the serial port is set at high level; (f) determining that the DTR pin and a ring indicator (RI) pin of the serial port work normally, upon the condition that the second status values indicate the voltages of the DTR pin and the RI pin are at high level; (g) acquiring a third status values of the serial port when the voltages of the RTS pin and DTR pin are set at high level; and (h) determining that a data send ready (DSR) pin and a clear to send (CTS) pin of the serial port work normally, upon the condition that the third status values indicate the voltages of the DSR pin and the CTS pin are at high level. ### Claim 15 (depends on 14) The non-transitory storage medium of claim 14, wherein the serial port electronically connects to a test fixture that comprises four npn transistors, and the four npn transistors connect to the serial port to form five circuit loops that comprise: a first circuit loop that is formed by connecting the TXD pin to the RXD pin; a second circuit loop that is formed by connecting the DTR pin to a base of a first transistor, connecting the RTS pin to a collector of the first transistor, and connecting the CTS pin to an emitter of the first transistor; a third circuit loop that is formed by connecting the TXD pin to a base of a second transistor, connecting the DTR pin to a collector of the second transistor, and connecting the RI pin to an emitter of the second transistor; a fourth circuit loop that is formed by connecting the IRIS pin to a base of a third transistor, connecting the DTR pin to a collector of the third transistor, and connecting the DSR pin to an emitter of the third transistor; and a fifth circuit loop that is formed by connecting the TXD pin to a base of a fourth transistor, connecting the RTS pin to a collector of the fourth transistor, and connecting the DCD pin to an emitter of the fourth transistors. ### Claim 16 (depends on 14) The non-transitory storage medium of claim 14, wherein the method further comprises: initializing the serial port according to predetermined configuration information. ### Claim 17 (depends on 14) The non-transitory storage medium of claim 14, wherein the step (d) comprises: determining that the RTS pin and the DCD pin do not work normally, upon the condition that the first status values indicate the voltages of the RTS pin and the DCD pin are not at high level. ### Claim 18 (depends on 14) The non-transitory storage medium of claim 14, wherein the step (f) comprises: determining that the DTR pin and the RI pin do not work normally, upon the condition that the second status values indicate the voltages of the DTR pin and the RI pin are not at high level. ### Claim 19 (depends on 14) The non-transitory storage medium of claim 14, wherein the step (h) comprises: determining that the DSR pin and the CTS pin do not work normally, upon the condition that the third status values indicate the voltages of the DSR pin and the CTS pin are not at high levels.