High-speed data reception circuitry and methods

A method of equalizing an input signal comprising:

• providing from control circuitry a first coefficient value to a first input of a selection circuit and logic circuitry, wherein the first coefficient value changes as the control circuitry is adapting a first time to the input signal;
• providing from the logic circuitry a second coefficient value to a second input of the selection circuit, wherein the second coefficient value is equal to a value of the changing first coefficient value last received by the logic circuitry;
• providing from buffer circuitry, coupled between an input of the control circuitry and the input signal, an error signal that indicates an amount of deviation of characteristics of the input signal and reference characteristics to the control circuitry;
• selecting the first input for use in equalizing the input signal while the control circuitry is adapting to the input signal;
• selecting the second input for use in equalizing the input signal when a first indication of stability is received by the logic circuitry;
• and
• applying a third coefficient value that corresponds to the second coefficient value to a decision-feedback equalization that is disabled while the control circuitry is adapting a first time to the input signal when the indication of stability is received by the logic circuitry.

A programmable logic device comprising:

• programmable logic circuitry;
• and
• selection circuitry operative to select either a first coefficient value received from control circuitry while the control circuitry is adapting to a serial data signal or a second coefficient value received from the programmable logic circuitry when an indication of stability is received by the programmable logic circuitry, wherein:
• buffer circuitry, coupled between an input of the control circuitry and the serial data signal, provides an error signal that indicates an amount of deviation of characteristics of the input signal and reference characteristics to the control circuitry;
• the first coefficient value changes as the control circuitry adapts to the serial data signal;
• the control circuitry provides the changing first coefficient value to the logic circuitry;
• and
• the second coefficient value is equal to a value of the changing first coefficient value last received by the logic circuitry when the logic circuitry received the indication of stability, wherein a third coefficient value that corresponds to the second coefficient value is applied to a decision-feedback equalization that is disabled while the control circuitry is adapting a first time to the input signal when the indication of stability is received by the logic circuitry.