# US 8,739,401 B2 · Circuit member, manufacturing method for circuit members, semiconductor device, and surface lamination structure for circuit member

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- Number: US 8,739,401 B2
- Document ID: US8739401B2
- Status: Granted
- Kind: B2
- Application number: 12/878,137
- Filed: 2010-09-09
- Published: 2010-12-30
- Granted: 2014-06-03
- Earliest claimed: 2005-04-26
- Assignees: Dai Nippon Printing Co., Ltd.
- Applicants: Yo Shimazaki; Hiroyuki Saito; Masachika Masuda; Kenji Matsumura; Masaru Fukuchi; Takao Ikezawa
- Inventors: Yo Shimazaki; Hiroyuki Saito; Masachika Masuda; Kenji Matsumura; Masaru Fukuchi; Takao Ikezawa
- Web page: https://patentgrep.com/patent/US8739401B2

## CPC

- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)}
- H10W 70/457: {of metallic layers on leadframes}
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H10W 72/0198: {batch processes}
- H10W 72/07353: {changes in shapes}
- H10W 72/075: {of bond wires}
- H10W 72/334: {Cross-sectional shape, i.e. in side view}
- H10W 72/50: Bond wires
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/931: {Shapes of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- Y10T 29/49121: Beam lead frame or beam lead device
- Y10T 29/49124: On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T 29/4913: Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T 29/49155: Manufacturing circuit on or in base
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.

## Claims

### Claim 1

A manufacturing method for circuit members, comprising:
forming a frame substrate with a die pad portion and a lead portion, by patterning a rolled copper plate or a rolled copper alloy plate;
roughing upside surfaces and lateral wall surfaces of the frame substrate, using a micro-etching solution having hydrogen peroxide and sulfuric acid as components, with a making material covering bottom surfaces of the frame substrate; and
after a removal of the masking material, laminating metallic skins on the roughed upper surfaces, the roughed lateral wall surfaces and the bottom surface of the frame substrate simultaneously so that the metallic skins on roughed upper surfaces and the roughed lateral wall surfaces of the frame substrate have needle-shaped projections.

### Claim 2 (depends on 1)

The manufacturing method for circuit members as claimed in claim 1, wherein the step of laminating the metallic skins comprises laminating an Ag skin on an obverse surface of the frame substrate.

### Claim 3 (depends on 1)

The manufacturing method for circuit members as claimed in claim 1, wherein the step of laminating the metallic skins comprises laminating a Ni skin and a Pd skin in order on an obverse surface of the frame substrate.

### Claim 4 (depends on 3)

The manufacturing method for circuit members as claimed in claim 3, comprising laminating an Au skin on the Pd skin.

### Claim 5

A manufacturing method for circuit members, comprising:
forming a frame substrate with a die pad portion and a lead portion, by patterning a rolled copper plate or a rolled copper alloy plate;
laminating metallic skins on a semiconductor chip mounting portion of an upper surface of the die pad portion, and on a portion of the lead portion to be connected to a bonding wire;
roughing upper surfaces and lateral surfaces of the die pad portion and the lead portion so as to selectively maintain a smooth surface of the semiconductor chip mounting portion, using a micro-etching solution having hydrogen peroxide and sulfuric acid as principal components, with a masking material covering entire bottom surfaces of the die pad portion and the lead portion; and
removing the masking material.

### Claim 6

A manufacturing method for a semiconductor device, comprising:
forming a frame substrate with a die pad portion and a lead portion, by patterning a rolled copper plate or a rolled copper alloy plate;
roughing upper surfaces and lateral wall surfaces of the die pad portion and the lead portion, using a micro-etching solution having hydrogen peroxide and sulfuric acid as components, with a masking material covering bottom surfaces of the die pad portion and the lead portion and a part of the upper surfaces of the lead portion to be brought into contact with a resin sealing mold so as to maintain smooth surfaces;
after removal of the masking material, laminating metallic skins on obverse surfaces of the die pad portion and the lead portion;
mounting a semiconductor chip on the upper surface of the die pad portion;
connecting the semiconductor chip and the lead portion with a bonding wire; and
molding the semiconductor chip with a sealing resin by contacting a resin sealing mold to the smooth surfaces of the part of the part of the upper surfaces of the lead portion and the smooth surface of the die pad portion and the lead portion.

### Claim 7

A manufacturing method for a semiconductor device, comprising:
forming a frame substrate with a die pad portion and a lead portion, by patterning a rolled copper plate or a rolled copper alloy plate;
laminating metallic skins on an upper surface of the die pad portion, and on a portion of the lead portion to be connected to a bonding wire;
surface-roughing the die pad portion and the lead portion, using a micro-etching solution having hydrogen peroxide and sulfuric acid as principal components, with a masking material covering bottom surfaces of the die pad portion and the lead portion having the metallic skins laminated thereon and a part of the upper surfaces of the lead portion to be brought into contact with a resin sealing mold so as to maintain smooth surfaces;
removing the masking material;
mounting a semiconductor chip on the upper surface of the die pad portion;
connecting the semiconductor chip and the lead portion with a bonding wire; and
molding the semiconductor chip with a sealing resin by contacting a resin sealing mold to the smooth surfaces of the part of the upper surfaces of the lead portion and the smooth surfaces of the bottom surfaces of the die pad portion and the lead portion.