Methods of patterning small via pitch dimensions

An integrated circuit method, comprising:

• forming a patterned resist layer on a substrate having a peanut shaped opening;
• forming a spacer on sidewalls of the peanut shaped opening of the patterned resist layer such that the spacer fills in a necking portion of the peanut shaped openings, resulting in two separate openings defined by the patterned resist layer and the spacer;
• and
• performing an etch process to the substrate through the two separate openings using the patterned resist layer and the spacer as a combined etch mask.

An integrated circuit (IC) method, comprising:

• receiving an IC design layout for an integrated circuit with via patterns;
• adding an optical proximity correction (OPC) feature on the IC design layout to link at least two adjacent via patterns with the OPC feature, forming a modified IC design layout;
• making a photomask using the modified IC design layout;
• forming a dielectric material layer on a substrate;
• forming, on the dielectric material layer, a hard mask having two openings that define trench lines;
• forming a patterned resist layer on the hard mask using the photomask, wherein the patterned resist layer includes a peanut shaped opening with two end portions overlapped with the two openings;
• and
• performing a first etch process to the dielectric material layer using the hard mask and the patterned resist layer as a combined etch mask.