Adjustable pole and zero location for a second order low pass filter used in a phase lock loop circuit

A phase lock loop feedback circuit, comprising:

• a phase frequency detector circuit having a first input port configured to receive an first clock signal and a second input port configured to receive a second clock signal, the phase frequency detector circuit being configured to compare the first clock signal with the second clock signal to generate a comparing result signal;
• a charge pump circuit configured to receive the comparing result signal and generate a current signal;
• a loop filter coupled to the charge pump having an input node for receiving the current signal and an output node for outputting a voltage signal, wherein the loop filter comprising:
• a first resistor connected to the input node;
• a first capacitor;
• a second resistor connected between the first resistor and the first capacitor;
• and
• a differential amplifier having a first input terminal, a second input terminal and an output terminal, the first input terminal being directly connected to the input node and coupled to the output node, the second input terminal being connected to the input node through the first resistor, and the output terminal being connected to the first capacitor;
• a voltage controlled oscillator coupled to the output node for generating a third clock signal according to the voltage signal from the loop filter, and
• a frequency divider coupled to the voltage controlled oscillator for dividing the third clock signal and generating a fourth clock signal, the fourth clock signal being sent to the second input port of the phase frequency detector circuit.