Tools and methods for yield-aware semiconductor manufacturing process target generation

An integrated circuit having at least one array of circuit cells, each circuit cell in the circuit cell array designed using a plurality of transistors each of which performs a specified function, the transistors each having a predefined performance parameter margin for the specified function, the circuit cells designed according to a computer implemented method including the steps of:

• providing at least one targeted operating condition for the bit cell array;
• providing, using a factorial design of experiments, a value of circuit level sigma over a predefined range;
• determining for each transistor, at least one variable transistor characteristic, the transistor characteristic defined by a semiconductor process that results in a transistor having such transistor characteristic;
• providing an array of instances based upon the value of the circuit level sigma;
• providing a metric of interest by which to determine pass and failure instances;
• extracting individual pass and fail instances for the metric of interest;
• and
• determining a yield for the array of circuit cells for the targeted operating condition.

A computer program product including a non-transitory computer-readable medium having instructions stored thereon that, if executed by a computing device, cause the computing device to perform operations for designing a circuit cell, the instructions comprising:

• providing at least one targeted operating condition for the bit cell array;
• providing a factorial design of experiments a value of circuit level sigma over a predefined range;
• determining for each transistor, at least one variable transistor characteristic, the transistor characteristic defined by a semiconductor process that results in a transistor having such transistor characteristic;
• providing an array of instances based upon the value of the circuit level sigma;
• providing a metric of interest by which to determine pass and failure instances;
• extracting individual pass and fail instances for the metric of interest;
• and
• determining a yield for the array of circuit cells for the targeted operating condition.