Method and apparatus for efficiently inserting fills in an integrated circuit layout
AssigneeCadence Design Systems, Inc.
InventorDavid C. Noice
Life of this patent
Estimating the term…
Abstract
A method for efficiently producing a design layout that includes several fills between and around nets of the design layout is described. The method of some embodiments first places a set of fills in the design layout. The method then performs a timing analysis on the design layout to find out the impact of the fills on the timing of the nets. The method identifies a region of the design layout in which to trim a set of fills in order to fix any timing violations of the nets. The method then trims the set of fills in the identified region. In some embodiments, the method employs different trimming strategies for trimming fills around different nets based on the characteristics of the nets.
Claims33
A computer-implemented method for placing fills in a circuit design layout comprising a plurality of nets, the method comprising:
- placing a plurality of fills in the circuit design layout;
- identifying a set of critical nets;
- and
- for each critical net in the set of critical nets:
- at a computer, identifying a trimming distance based on a property of the critical net;
- and
- trimming fills within the identified trimming distance around the critical net.
A non-transitory machine readable medium storing a program that when executed by at least one processing unit places fills in a circuit design layout comprising a plurality of nets, the program comprising sets of instructions for:
- placing a plurality of fills in the circuit design layout;
- identifying a critical net;
- and
- identifying different trimming distances for different portions of the critical net;
- and
- for each portion of the critical net, trimming fills within the identified trimming distance around the portion of the critical net without violating a set of design rules.
A system comprising:
- a processor for executing sets of instructions;
- and
- a memory for storing a computer program for placing fills in a circuit design layout including a plurality of shapes, the program comprising sets of instructions for:
- placing a plurality of fills in the circuit design layout;
- performing, after placing the fills, a timing analysis for the circuit design layout;
- selecting a net based on a result of the timing analysis;
- identifying a trimming region around the net based on properties of the selected net;
- and
- trimming fills within the identified trimming region around the selected net in the circuit design layout.
A computer-implemented method for trimming fills in a circuit design layout comprising a plurality of nets and a plurality of fills, the method comprising:
- at a computer, performing a timing analysis for the circuit design layout to identify properties of the plurality of nets;
- selecting a net based on the properties identified by the timing analysis;
- defining a region around the selected net;
- and
- trimming a set of fills in the circuit layout within the defined region.
Dependencies are inferred from the claim text.