System and method for employing signoff-quality timing analysis information concurrently in multiple scenarios to reduce dynamic power in an electronic circuit and an apparatus incorporating the same

A dynamic power recovery method carried out in each of multiple scenarios concurrently, comprising:

• making first conditional downsizing of cells in at least one path in a circuit design with lower dynamic power cells, wherein said lower dynamic power cells have an internal capacitance that is less than an internal capacitance of said cells first conditionally downsize;
• estimating a delay and a slack of said at least one path based on said first conditional downsizing;
• determining whether said first conditional downsizings cause a timing violation with respect to said at least one path;
• making second conditional upsizings with higher dynamic power cells until said timing violation is removed;
• and
• merging and applying said downsizings and upsizings and updating timing with respect to said each of said multiple scenarios, wherein said determining is performed by a processor.

An apparatus, comprising:

• circuitry for making first conditional downsizing of cells in at least one path in a circuit design with lower dynamic power cells, wherein said lower dynamic power cells have an internal capacitance that is less than an internal capacitance of said cells first conditionally downsized;
• circuitry for estimating a delay and a slack of said at least one path based on said first conditional downsizing;
• circuitry for determining whether said first conditional downsizings cause a timing violation with respect to said at least one path;
• circuitry for making second conditional upsizings with higher dynamic power cells until said timing violation is removed;
• and
• circuitry for merging and applying said downsizings and upsizings and updating timing with respect to said each of said multiple scenarios.