Assisting apparatus, method, and program for checking crosstalk noise between hierarchized modules in a semiconductor circuit

A design assisting method comprising:

• referencing, by a processor, routing information representing a first wire line from wire lines of a module belonging to a first layer of a semiconductor circuit having a plurality of layers, the module having a first layout area, the first wire line being likely to become either one of an aggressor net and a victim net in a crosstalk noise check performed on wire lines of a supra-chip, the supra-chip being a module belonging to a second layer hierarchically higher than the first layer, the first layout area being within a second layout area of the supra-chip;
• identifying a second wire line within the supra-chip of the first module, the second wire line being likely to become either one of an aggressor net and a victim net in the crosstalk noise check performed on the first wire line represented by the routing information stored on the memory, the second wire line being an aggressor net when the first wire line is a victim net and a victim net when the first wire line is an aggressor net, the processor performing the wire line identification for the first module separately and in parallel with the wire line identification for a second module, the second module not being a supra-chip of the first module, the first module not being a supra-chip of the second module;
• determining whether an interface file belonging to a layer lower than a sub chip as a check target is present;
• reading the interface file of sub chips of all lower layers when a determination is made that the interface file is present;
• and
• outputting information of the identified wire line.

A computer-readable, non-transitory storage medium storing therein a design assisting program that causes a computer to execute a process, the process comprising:

• referencing, by a processor, routing information representing a first wire line from wire lines of a module belonging to a first layer of a semiconductor circuit having a plurality of layers, the module having a first layout area, the first wire line being likely to become either one of an aggressor net and a victim net in a crosstalk noise check performed on wire lines of a supra-chip, the supra-chip being a module belonging to a second layer hierarchically higher than the first layer, the first layout area being within a second layout area of the supra-chip;
• identifying a second wire line within the supra-chip of the first module, the second wire line being likely to become either one of an aggressor net and a victim net in the crosstalk noise check performed on the first wire line represented by the routing information stored on the memory, the second wire line being an aggressor net when the first wire line is a victim net and a victim net when the first wire line is an aggressor net, the processor performing the wire line identification for the first module separately and in parallel with the wire line identification for a second module, the second module not being a supra-chip of the first module, the first module not being a supra-chip of the second module;
• determining whether an interface file belonging to a layer lower than a sub chip as a check target is present;
• and
• reading the interface file of sub chips of all lower layers when a determination is made that the interface file is present;
• and
• outputting information of the identified wire line.