Methods and systems to reduce a number of simulations in a timing analysis
AssigneeInternational Business Machines Corporation
InventorsNilesh C. Date, Amol A. Joshi, David B. White, William J. Wright
Life of this patent
Estimating the term…
Loading patent…
AssigneeInternational Business Machines Corporation
InventorsNilesh C. Date, Amol A. Joshi, David B. White, William J. Wright
Estimating the term…
Methods and systems for determining timing constraint analysis of an integrated circuit (IC) may include defining a sequence of sample points for timing constraint analysis of an n×n matrix, each sample point corresponding to a timing arc of the IC that includes data and reference slews; initially simulating extreme sample points of the matrix, according to the sequence, by substituting timing constraints from liberty files of the IC type for time values of the data slews and conducting a binary search for optimized timing constraints; and interpolating other sample points, according to the sequence, each of the other sample points having a starting bisection point that results from linear interpolation of the timing constraint analysis from adjoining sample points, which were simulated.
A computer-implemented method for determining timing constraint analyses of an integrated circuit (IC), said method comprising:
A computer-implemented method for determining timing constraint analyses of an integrated circuit (IC), said method comprising:
A tangible computer program product readable by computer, tangibly embodying a program of instructions executable by said computer to perform a method for determining timing constraint analyses of an integrated circuit (IC), said method comprising:
Dependencies are inferred from the claim text.