Dual-box location aware and dual-bitmap voltage domain aware on-chip variation techniques
AssigneeSynopsys, Inc.
InventorsJiayong Le, Feroze P. Taraporevala
Life of this patent
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Abstract
A dual-box location-based on-chip variation (DBLOCV) can be used in STA to significantly reduce pessimism. The DBLOCV analysis includes forming a backward bounding box and a forward bounding box for a cell of the design. A first intermediate maximum distance from the cell to corners of the backward bounding box can be calculated using the coordinates. A second intermediate maximum distance from the cell to corners of the forward bounding box can be calculated using the coordinates. A derate value can be determined from the derate table using the maximum distance of the first and second intermediate maximum distances. STA can be performed using the derate value. At least one timing report can be generated based on the STA.
Claims23
A method of performing static timing analysis (STA), the method comprising:
- reading a design of an integrated circuit, the design being at least placed;
- determining coordinates of cells of the design;
- reading in a derate table;
- performing dual-box location-based on-chip variation (DBLOCV) analysis, the DBLOCV analysis including:
- forming a backward bounding box and a forward bounding box for a cell;
- calculating a first intermediate maximum distance from the cell to corners of the backward bounding box using the coordinates;
- calculating a second intermediate maximum distance from the cell to corners of the forward bounding box using the coordinates;
- determining a derate value for the cell from the derate table using a maximum distance of the first and second intermediate maximum distances;
- performing the STA using the derate value for the cell;
- and
- generating at least one timing report based on the STA.
A method of performing dual-box location-based on-chip variation (DBLOCV) analysis, the DBLOCV analysis including:
- forming a backward bounding box and a forward bounding box for a cell of a design;
- calculating a first intermediate maximum distance from the cell to corners of the backward bounding box using coordinates of the design;
- calculating a second intermediate maximum distance from the cell to corners of the forward bounding box using the coordinates;
- and
- determining a derate value using a maximum distance of the first and second intermediate maximum distances,
- wherein the method is performed by a computer.
A non-transitory, computer-readable medium storing computer-executable instructions for performing static timing analysis (STA), the instructions when executed by a processor cause the processor to execute a process comprising:
- reading a design of an integrated circuit, the design being at least placed;
- determining coordinates of cells of the design;
- reading in a derate table;
- performing dual-box location-based on-chip variation (DBLOCV) analysis, the DBLOCV analysis including:
- forming a backward bounding box and a forward bounding box for a cell;
- calculating a first intermediate maximum distance from the cell to corners of the backward bounding box using the coordinates;
- calculating a second intermediate maximum distance from the cell to corners of the forward bounding box using the coordinates;
- determining a derate value from the derate table using a maximum distance of the first and second intermediate maximum distances;
- performing the STA using the derate value;
- and
- generating at least one timing report based on the STA.
A computer program product comprising an electronic design automation (EDA) program to be executed by a computer, the EDA program for performing a process comprising:
- reading a design of an integrated circuit, the design being at least placed;
- determining coordinates of cells of the design;
- reading in a derate table;
- using the computer, performing dual-box location-based on-chip variation (DBLOCV) analysis, the DBLOCV analysis including:
- forming a backward bounding box and a forward bounding box for a cell;
- calculating a first intermediate maximum distance from the cell to corners of the backward bounding box using the coordinates;
- calculating a second intermediate maximum distance from the cell to corners of the forward bounding box using the coordinates;
- determining a derate value from the derate table using a maximum distance of the first and second intermediate maximum distances;
- performing static timing analysis (STA) using the derate value;
- and
- generating at least one timing report based on the STA.
A method of performing static timing analysis (STA), the method comprising:
- reading a design of an integrated circuit, the design being at least placed;
- determining coordinates of cells of the design;
- reading in a derate table;
- performing advanced location-based on-chip variation (ALOCV) analysis, the ALOCV analysis including calculating four distances from a cell to four corners of a bounding box including the cell using the coordinates;
- determining a derate value from the derate table using a maximum distance of the four distances;
- performing the STA using the derate value;
- and
- generating at least one timing report based on the STA.
A method of performing advanced location-based on-chip variation (ALOCV) analysis, the ALOCV analysis comprising:
- calculating four distances from a cell to four corners of a bounding box including the cell, the calculating using coordinates of a design including the cell;
- and
- determining a derate value using a maximum distance of the four distances,
- wherein the method is performed using a computer.
A non-transitory, computer-readable medium storing computer-executable instructions for performing static timing analysis (STA), the instructions when executed by a processor cause the processor to execute a process comprising:
- reading a design of an integrated circuit, the design being at least placed;
- determining coordinates of cells of the design;
- reading in a derate table;
- performing dual-box location-based on-chip variation (DBLOCV) analysis, the DBLOCV analysis including calculating four distances from a cell to four corners of a bounding box including the cell using the coordinates;
- determining a derate value from the derate table using a maximum distance of the four distances;
- performing the STA using the derate value;
- and
- generating at least one timing report based on the STA.
A computer program product comprising an electronic design automation (EDA) program to be executed by a computer, the EDA program for performing steps comprising:
- reading a design of an integrated circuit, the design being at least placed;
- determining coordinates of cells of the design;
- reading in a derate table;
- using the computer, performing dual-box location-based on-chip variation (DBLOCV) analysis, the DBLOCV analysis including calculating four distances from a cell to four corners of a bounding box including the cell using the coordinates;
- determining a derate value from the derate table using a maximum distance of the four distances;
- performing static timing analysis (STA) using the derate value;
- and
- generating at least one timing report based on the STA.
A method of performing static timing analysis (STA), the method comprising:
- reading a design of an integrated circuit;
- determining voltage domains of cells of the design;
- performing multiple voltage domain analysis, the multiple voltage domain analysis including generating forward bitmaps and backward bitmaps for a plurality of cells of the design;
- from an end-point cell of the design, identifying a common point cell, the plurality of cells including the end-point cell and the common point cell;
- calculating an intersection of a forward bitmap of the common point cell and a backward bitmap of the end-point cell;
- identifying any voltage domain that is not on a common clock path based on the intersection, the identifying generating at least two identified voltage domains;
- performing the STA with the multiple voltage domain analysis based on the at least two identified voltage domains;
- and
- generating at least one timing report based on the STA.
A non-transitory, computer-readable medium storing computer-executable instructions for performing static timing analysis (STA), the instructions when executed by a processor cause the processor to execute a process comprising:
- reading a design of an integrated circuit;
- determining voltage domains of cells of the design;
- performing multiple voltage domain analysis, the multiple voltage domain analysis including generating forward bitmaps and backward bitmaps for a plurality of cells of the design;
- from an end-point cell of the design, identifying a common point cell, the plurality of cells including the end-point cell and the common point cell;
- calculating an intersection of a forward bitmap of the common point cell and a backward bitmap of the end-point cell;
- identifying any voltage domain that is not on a common clock path based on the intersection, the identifying generating at least two identified voltage domains;
- performing the STA with the multiple voltage domain analysis based on the at least two identified voltage domains;
- and
- generating at least one timing report based on the STA.
A computer program product comprising an electronic design automation (EDA) program, the EDA program for performing a process comprising:
- reading a design of an integrated circuit;
- determining voltage domains of the design;
- performing multiple voltage domain analysis, the multiple voltage domain analysis including generating forward bitmaps and backward bitmaps for a plurality of cells of the design;
- from an end-point cell of the design, identifying a common point cell, the plurality of cells including the end-point cell and the common point cell;
- calculating an intersection of a forward bitmap of the common point cell and a backward bitmap of the end-point cell;
- identifying any voltage domain that is not on a common clock path based on the intersection, the identifying generating at least two identified voltage domains;
- performing the STA with the multiple voltage domain analysis based on the at least two identified voltage domains;
- and
- generating at least one timing report based on the STA.
Dependencies are inferred from the claim text.