Method of generating integrated circuit model
AssigneeRealtek Semiconductor Corp.
InventorsMeng-Jung Lee, Ting-Hsiung Wang, Yu-Lan Lo, Shu-Yi Kao
Life of this patent
Estimating the term…
Abstract
An integrated circuit test model is generated according to a circuit connection net-list, an isolation cell topology, and a pin voltage information spec file, so that the procedure of generating the integrated circuit test model can be time-saving, efficient, and fool-proof. Besides, while tracing a current path of a node of the circuit connection net-list, the generated integrated circuit test model can be more precise if certain limitations are added.
Claims9
A non-transitory computer readable medium storing computer program instructions that, when executed by a microprocessor, cause the microprocessor to perform a method of generating an integrated circuit model, comprising:
- generating, with the microprocessor, a circuit isolation node file according to a circuit connection net-list and an isolation cell topology, comprising:
- executing at least one first instruction included by an instruction set program and taking the circuit connection net-list and the isolation cell topology as arguments of executing the at least one first instruction for generating the circuit isolation node file;
- generating an interface node voltage net-list according to the circuit connection net-list and a pin voltage spec file, comprising:
- executing at least one second instruction included by the instruction set program and taking the circuit connection net-list and the pin voltage spec file as arguments of executing the at least one second instruction for generating the interface node voltage net-list;
- and
- generating an integrated circuit voltage model according to the circuit isolation node file and the interface node voltage net-list.
A non-transitory computer readable medium storing computer program instructions that, when executed by a microprocessor, cause the microprocessor to perform a method of generating an integrated circuit model, comprising:
- generating, with the microprocessor, a circuit isolation node file according to a circuit connection net-list and an isolation cell topology;
- generating an interface node voltage net-list according to the circuit connection net-list and a pin voltage spec file, comprising:
- tracing a current path started from a node included by the circuit connection net-list on the circuit connection net-list, and determining a power source node and a ground node both corresponding to the node according to voltage specs of each node included by the circuit connection net-list recorded in the pin voltage spec file;
- and
- recording the node along with the power source node and the ground node for generating the interface node voltage net-list;
- and
- generating an integrated circuit voltage model according to the circuit isolation node file and the interface node voltage net-list.
A non-transitory computer readable medium storing computer program instructions that, when executed by a microprocessor, cause the microprocessor to perform a method of generating an integrated circuit model, comprising:
- generating, with the microprocessor, a circuit isolation node file according to a circuit connection net-list and an isolation cell topology, comprising:
- tracing a current path started from a node included by the circuit connection net-list on the circuit connection net-list, and confirming whether an isolation element is passed by the current path on the circuit connection net-list according to at least one isolation node and element connection characteristics of isolation elements recorded by the isolation cell topology;
- and
- recording the isolation element for generating the circuit isolation node file when the isolation element is confirmed to be passed by the current path on the circuit connection net-list;
- generating an interface node voltage net-list according to the circuit connection net-list and a pin voltage spec file;
- and
- generating an integrated circuit voltage model according to the circuit isolation node file and the interface node voltage net-list.
A non-transitory computer readable medium storing computer program instructions that, when executed by a microprocessor, cause the microprocessor to perform a method of generating an integrated circuit model, comprising:
- generating, with the microprocessor, a circuit isolation node file according to a circuit connection net-list and an isolation cell topology;
- generating an interface node voltage net-list according to the circuit connection net-list and a pin voltage spec file;
- generating an integrated circuit voltage model according to the circuit isolation node file and the interface node voltage net-list;
- determining simulation voltages of a plurality of node groups included by the interface node voltage net-list according to the interface node voltage net-list and the pin voltage spec file, wherein each of the plurality of node groups comprises a node and both a power source node and a ground node corresponding to the node;
- and
- generating an integrated circuit functional block test model according to the simulation voltages of the plurality of groups.
A non-transitory computer readable medium storing computer program instructions that, when executed by a microprocessor, cause the microprocessor to perform a method of generating an integrated circuit model, comprising:
- generating, with the microprocessor, a circuit isolation node file according to a circuit connection net-list and an isolation cell topology;
- generating an interface node voltage net-list according to the circuit connection net-list and a pin voltage spec file;
- and
- generating an integrated circuit voltage model according to the circuit isolation node file and the interface node voltage net-list, comprising:
- updating the interface node voltage net-list utilizing a power-off node file for generating an updated interface node voltage net-list;
- and
- generating an integrated circuit voltage test model according to the circuit isolation node file and the updated interface node voltage net-list.
Dependencies are inferred from the claim text.