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AssigneeLSI Corporation
InventorsPavel Aleksandrovich Aliseychik, Aleksey Alexandrovich Letunovskiy, Alexander Alexandrovich Petyushko, Denis Vladimirovich Parkhomenko, Alexander Borisovich Kholodenko
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A computer-aided design method for developing, simulating, and testing a read-channel architecture to be implemented in a VLSI circuit. The method uses a coset operating mode and nonzero-syndrome-based decoding to accelerate the simulation of the read-channel's error-rate characteristics corresponding to different parity-check matrices employed in the read-channel's turbo-decoder, such as a low-density parity-check decoder. The acceleration is achieved through recycling some previously generated log-likelihood-ratio values, which enables the method to sometimes bypass certain time-consuming processing steps therein.
A computer-aided design method comprising:
An integrated circuit fabricated using a computer-aided design method that comprises:
A non-transitory machine-readable medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a computer-aided design method, the computer-aided design method comprising:
Dependencies are inferred from the claim text.