Synthesizing VHDL multiple wait FSMS into RT level FSMS by preprocessing
AssigneeInternational Business Machines Corporation
InventorsGabor Bobok, Gabor Drasny, Ali El-Zein
Life of this patent
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Abstract
Preprocessing parallel sequences of “wait” statements and synthesizing these multiple “wait” statements to construct support for RTL tools. This is accomplished by preprocessing a VHDL process with multiple wait statements (referred to as BehFSM) into an equivalent register transfer.
Claims9
A method of preprocessing parallel sequences of “wait” statements and synthesizing these multiple “wait” statements in Hardware Design Language source code containing multiple wait statements into equivalent register transfer code target file with the target file being in lower to upper correct dependency order, comprising the steps of:
- a) creating a process statement and a case statement whose selection expression is a current state using a computer processor;
- b) initialize a wait state;
- c) locating a wait statement corresponding in position to the initialized wait state;
- d) creating an entry in a case statement in the code that corresponds to a behavioral model when a register transfer level wait state is in the initialized wait state;
- and
- e) incrementing the wait state number.
A computer system comprising a central processor, input means, output means, and memory, said computer system configured and controlled to carry out a method of preprocessing parallel sequences of “wait” statements and synthesizing these multiple “wait” statements in Hardware Design Language source code containing multiple wait statements into equivalent register transfer code target file, said method comprising the steps of:
- a) creating a process statement and a case statement whose selection expression is a current state;
- b) initialize a wait state;
- c) locating a wait statement corresponding in position to the initialized wait state;
- d) creating an entry in a case statement in the code that corresponds to a behavioral model when a register transfer level wait state is in the initialized wait state;
- and
- e) incrementing the wait state number.
A program product comprising non-transitory computer readable media having computer readable code thereon, said computer readable code adapted to control and configure a computer to perform a method comprising preprocessing parallel sequences of “wait” statements and synthesizing these multiple “wait” statements in Hardware Design Language source code containing multiple wait statements into equivalent register transfer code target file, comprising the steps of:
- a) creating a process statement and a case statement whose selection expression is a current state;
- b) initialize a wait state;
- c) locating a wait statement corresponding in position to the initialized wait state;
- d) creating an entry in a case statement in the code that corresponds to a behavioral model when a register transfer level wait state is in the initialized wait state;
- and
- e) incrementing the wait state number.
Dependencies are inferred from the claim text.