US 8,713,486 B2Granted

High performance design rule checking technique

AssigneeSynopsys, Inc.

InventorsZuo Dai, Dick Liu, Ming Su

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Abstract

Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously.

Claims40

Dependent claims

A method for checking a set of layout design rules on a region of an integrated circuit layout, the layout including a plurality of shapes each including edges in a plurality of different orientations, each of the edges having endpoints at respective locations in the layout, endpoints of edges in a first one of the orientations being first endpoints and endpoints of edges in a second one of the orientations being second endpoints,

for use by a computer system having access to a design rule data set indicating constraint values of design rules in the data set, the method comprising the steps of:
the computer system scanning the layout region in a first dimension which is perpendicular to the first edge orientation, so as to encounter first endpoints of the edges having the first orientation;
in response to encountering each of at least a first subset of at least two of the first endpoints, the computer system populating a layout topology database with values in dependence upon the respective first endpoint location;
the computer system scanning the layout region in a second dimension which is perpendicular to the second edge orientation, so as to encounter second endpoints of the edges having the second orientation;
in response to encountering each of at least a second subset of at least two of the second endpoints, the computer system populating the layout topology database with values in dependence upon the respective second endpoint location;
after the layout topology database has been populated with values in dependence upon the first endpoint location of all endpoints in the first subset of endpoints, and values in dependence upon the second endpoint location of all endpoints in the second subset of endpoints, the computer system comparing values in the layout topology database to values in the design rule data set to detect any violations of design rules in the set of design rules;
and
where a design rule violation is detected, reporting it to a user.

5 more elements

A system for checking a set of layout design rules on a region of an integrated circuit layout, the layout including a plurality of shapes each having shape corners at respective locations in the layout, comprising:

a computer system having access to a design rule data set indicating constraint values of design rules in the data set, the computer system further having access to computer instructions and data which, when applied to the computer system, perform the steps of:
scanning the layout region in a first dimension which is perpendicular to the first edge orientation, so as to encounter first endpoints of the edges having the first orientation;
in response to encountering each of at least a first subset of at least two of the first endpoints, the computer system populating a layout topology database with values in dependence upon the respective first endpoint location;
scanning the layout region in a second dimension which is perpendicular to the second edge orientation, so as to encounter second endpoints of the edges having the second orientation;
in response to encountering each of at least a second subset of at least two of the second endpoints, the computer system populating the layout topology database with values in dependence upon the respective second endpoint location;
after the layout topology database has been populated with values in dependence upon the first endpoint location of all endpoints in the first subset of endpoints, and values in dependence upon the second endpoint location of all endpoints in the second subset of endpoints, comparing values in the layout topology database to values in the design rule data set to detect any violations of design rules in the set of design rules;
and
where a design rule violation is detected, reporting it to a user.

5 more elements

A computer program product for checking a set of layout design rules on a region of an integrated circuit layout, the layout including a plurality of shapes each having shape corners at respective locations in the layout, for use by a computer system having access to a design rule data set indicating constraint values of design rules in the data set, the computer program product comprising

a non-transitory computer readable medium having stored thereon a plurality of software code portions and data which when executed by the computer system perform the steps of:
scanning the layout region in a first dimension which is perpendicular to the first edge orientation, so as to encounter first endpoints of the edges having the first orientation;
in response to encountering each of at least a first subset of at least two of the first endpoints, populating a layout topology database with values in dependence upon the respective first endpoint location;
scanning the layout region in a second dimension which is perpendicular to the second edge orientation, so as to encounter second endpoints of the edges having the second orientation;
in response to encountering each of at least a second subset of at least two of the second endpoints, populating the layout topology database with values in dependence upon the respective second endpoint location;
after the layout topology database has been populated with values in dependence upon the first endpoint location of all endpoints in the first subset of endpoints, and values in dependence upon the second endpoint location of all endpoints in the second subset of endpoints, comparing values in the layout topology database to values in the design rule data set to detect any violations of design rules in the set of design rules;
and
where a design rule violation is detected, reporting it to a user.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/718,527Filed 18 Dec 2012 · division
Priority: 3 Dec 2010
Published: US 2013/0159949 A120 Jun 2013
Granted: 29 Apr 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…
G06F 2111/04
Details relating to CAD techniques: constraint-based CAD
G06F
Computing and data processing

Family

Application12/960,086Parent of this division · filed 3 Dec 2010
US 2013/0159949 A1Pre-grant publication · published 20 Jun 2013
US 8,352,887 B2Parent of this division
US 2012/0144355 A1Published application
US 8,713,486 B2This patent

From the US filing history. Foreign family members aren’t listed.