Aware manufacturing of integrated circuits
AssigneeCadence Design Systems, Inc.
InventorsLouis K. Scheffer, Akira Fujimura
Life of this patent
Estimating the term…
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AssigneeCadence Design Systems, Inc.
InventorsLouis K. Scheffer, Akira Fujimura
Estimating the term…
Some embodiments of the invention provide a manufacturing aware process for designing an integrated circuit (“IC”) layout. The process receives a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture an IC based on the IC layout. The process defines a set of design rules based on the specified manufacturing configuration. The process uses the set of design rules to design the IC layout. Some embodiments of the invention provide a design aware process for manufacturing an integrated circuit (“IC”). The process receives an IC design with an associated set of design properties. The process specifies a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture the IC, where the specified set of manufacturing settings are based on the set of design properties. The process manufactures the IC based on the manufacturing settings.
A non-transitory computer readable medium storing a computer program that when executed by at least one processor performs a design aware process to manufacture an integrated circuit (“IC”) layout, the computer program comprising sets of instructions for:
A system comprising:
A non-transitory computer readable medium storing a computer program that when executed by at least one processor performs a design aware process to manufacture an integrated circuit (“IC”) layout, the computer program comprising sets of instructions for:
Dependencies are inferred from the claim text.