Multi-channel memory system including error correction decoder architecture with efficient area utilization
AssigneeSamsung Electronics Co., Ltd.
InventorNamphil Jo
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AssigneeSamsung Electronics Co., Ltd.
InventorNamphil Jo
Estimating the term…
A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.
A memory system, comprising:
A memory system, comprising:
A method of processing data received in a memory controller from first and second memory devices, the method comprising:
An error decoder used in a memory controller to correct errors in encoded data read from first and second memory devices during a read operation, the error decoder comprising:
Dependencies are inferred from the claim text.
From the US filing history. Foreign family members aren’t listed.
This claims priority under 35 U.S.C. §119 from Korean Patent Application 10-2007-0086515, filed on 28 Aug. 2007 in the name of Namphil Jo, the entirety of which is hereby incorporated by reference for all purposes as if fully set forth herein.
1. Field
This invention pertains to the field of memory systems, and more particularly, to the field of memory systems employing error correction decoding.
FIG. 1 shows a block diagram of a flash memory system.
FIG. 2 illustrates connections between an error correction coder (ECC) block and memory devices.
FIG. 3 illustrates a block diagram of one embodiment of a flash memory error correction coder (ECC) block that can operate in a two channel memory system.
FIG. 3 illustrates a block diagram of one embodiment of a flash memory error correction coder (ECC) block 300 that can operate in a two channel memory system. ECC block 300 is a Bose-Chaudhuri-Hocquenghem (BCH) error correction coder.
ECC block 300 includes two data encoders 361, one each for the first and second communication channels. ECC block 300 also includes two syndrome computation blocks 310a and 310b, again one for each of the first and second communication channels. ECC block 300 further includes a multiplexer (or data switch) 315, a key equation solver (KES) block 320, Chien search and error evaluator blocks 330 and 335, and a decoder controller 340.
In operation, ECC block 300 communicates data with memory devices (e.g., flash memory devices) over two communication channels operating at the same time as each other in parallel. When data from a host device (e.g., a processor) is to be written to the memory devices via the two communication channels, the data is first encoded (e.g. with a BCH code) by a corresponding encoder 361 for each communication channel. Then, the encoded data is transmitted in parallel across the two communication channels to the memory devices.
In individual solid state devices: in sector programmable memories, e.g. flash disk
Computing and data processing
About 5 years 4 months of term left · ends 7 Mar 2032 (estimated)