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US 8,713,416 B2Granted
Performing a cyclic redundancy checksum operation responsive to a user-level instruction
AssigneeIntel Corporation
InventorsSteven R. King, Frank Berry, Michael E. Kounavis
Life of this patent
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Abstract
In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.
Claims19
A processor comprising:
- a first register to store a first operand including a first plurality of bytes;
- a second register to store a second operand including a second plurality of bytes;
- and
- an execution unit coupled to the first register and the second register to perform an exclusive-OR (XOR) operation on at least one of the first plurality of bytes of the first operand and at least one of the second plurality of bytes of the second operand, and to store a result of the XOR operation in a destination register, wherein the processor is to perform the XOR operation responsive to a user-level instruction of an instruction set architecture (ISA) in one of a plurality of separate logic blocks each to perform the XOR operation on data of a different size.
1 more element
A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
- receiving a user-level instruction for a checksum operation in a processor, the user-level instruction specifying a source operand of a first size and a destination operand of a second size;
- receiving the source operand and the destination operand in the processor;
- and
- performing the checksum operation using the source operand and the destination operand in the processor responsive to the instruction, the processor having a plurality of hardware engines each to perform the checksum operation for one of a plurality of data sizes.
1 more element
A system comprising:
- a processor including logic to perform a cyclic redundancy check (CRC) instruction, wherein the logic is to perform the CRC instruction on a variable number of data sizes;
- a dynamic random access memory (DRAM) coupled to the processor;
- and
- a first processor core including a data path having a plurality of execution units, one of the execution units including the logic having a plurality of logic blocks, each of the logic blocks to perform the CRC instruction on data of one of the variable number of data sizes.
1 more element
Dependencies are inferred from the claim text.